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AD9434: Initial check in of the library and project with ZC706

main
Istvan Csomortani 2014-09-24 18:27:17 +03:00
parent 1d4bc47cea
commit 683561b67d
11 changed files with 1678 additions and 0 deletions
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library/axi_ad9434/axi_ad9434.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9434 (
// physical interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// delay interface
delay_clk,
// dma interface
adc_clk,
adc_dwr,
adc_data,
adc_dovf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
localparam SERIES7 = 0;
localparam SERIES6 = 1;
parameter PCORE_ID = 0;
parameter PCORE_DEVTYPE = SERIES7;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
// physical interface
input adc_clk_in_p;
input adc_clk_in_n;
input [11:0] adc_data_in_p;
input [11:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_dwr;
output [63:0] adc_data;
input adc_dovf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire mmcm_rst;
wire up_clk;
wire adc_clk;
wire drp_clk;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire adc_status_s;
wire delay_rst_s;
wire delay_sel_s;
wire delay_rwn_s;
wire [ 7:0] delay_addr_s;
wire [ 4:0] delay_wdata_s;
wire [ 4:0] delay_rdata_s;
wire delay_ack_t_s;
wire delay_locked_s;
wire drp_sel_s;
wire drp_rst_s;
wire drp_wr_s;
wire [11:0] drp_addr_s;
wire [15:0] drp_wdata_s;
wire [15:0] drp_rdata_s;
wire drp_ready_s;
wire drp_locked_s;
wire [11:0] adc_data_s0_s;
wire adc_or_s0_s;
wire [11:0] adc_data_s1_s;
wire adc_or_s1_s;
wire [11:0] adc_data_s2_s;
wire adc_or_s2_s;
wire [11:0] adc_data_s3_s;
wire adc_or_s3_s;
// clock/reset assignments
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign drp_clk = up_clk;
axi_ad9434_if #(
.PCORE_DEVTYPE(PCORE_DEVTYPE),
.PCORE_IODELAY_GROUP(PCORE_IODELAY_GROUP))
i_if(
.adc_clk_in_p(adc_clk_in_p),
.adc_clk_in_n(adc_clk_in_n),
.adc_data_in_p(adc_data_in_p),
.adc_data_in_n(adc_data_in_n),
.adc_or_in_p(adc_or_in_p),
.adc_or_in_n(adc_or_in_n),
.adc_data_s0(adc_data_s0_s),
.adc_or_s0(adc_or_s0_s),
.adc_data_s1(adc_data_s1_s),
.adc_or_s1(adc_or_s1_s),
.adc_data_s2(adc_data_s2_s),
.adc_or_s2(adc_or_s2_s),
.adc_data_s3(adc_data_s3_s),
.adc_or_s3(adc_or_s3_s),
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_status(adc_status_s),
.delay_clk(delay_clk),
.delay_rst(delay_rst_s),
.delay_sel(delay_sel_s),
.delay_rwn(delay_rwn_s),
.delay_addr(delay_addr_s),
.delay_wdata(delay_wdata_s),
.delay_rdata(delay_rdata_s),
.delay_ack_t(delay_ack_t_s),
.delay_locked(delay_locked_s),
.mmcm_rst(mmcm_rst),
.drp_clk(drp_clk),
.drp_rst(drp_rst_s),
.drp_sel(drp_sel_s),
.drp_wr(drp_wr_s),
.drp_addr(drp_addr_s),
.drp_wdata(drp_wdata_s),
.drp_rdata(drp_rdata_s),
.drp_ready(drp_ready_s),
.drp_locked(drp_locked_s));
// common processor control
axi_ad9434_core #(.PCORE_ID(PCORE_ID))
i_core (
.adc_clk(adc_clk),
.adc_data_s0(adc_data_s0_s),
.adc_or_s0(adc_or_s0_s),
.adc_data_s1(adc_data_s1_s),
.adc_or_s1(adc_or_s1_s),
.adc_data_s2(adc_data_s2_s),
.adc_or_s2(adc_or_s2_s),
.adc_data_s3(adc_data_s3_s),
.adc_or_s3(adc_or_s3_s),
.mmcm_rst (mmcm_rst),
.adc_rst (adc_rst),
.adc_status (adc_status_s),
.adc_valid (adc_dwr),
.adc_data (adc_data),
.adc_dovf (adc_dovf),
.delay_clk (delay_clk),
.delay_rst (delay_rst_s),
.delay_sel (delay_sel_s),
.delay_rwn (delay_rwn_s),
.delay_addr (delay_addr_s),
.delay_wdata (delay_wdata_s),
.delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s),
.drp_clk (drp_clk),
.drp_rst (drp_rst_s),
.drp_sel (drp_sel_s),
.drp_wr (drp_wr_s),
.drp_addr (drp_addr_s),
.drp_wdata (drp_wdata_s),
.drp_rdata (drp_rdata_s),
.drp_ready (drp_ready_s),
.drp_locked (drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
endmodule

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library/axi_ad9434/axi_ad9434_core.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9434_core (
// device interface
adc_clk,
adc_data_s0,
adc_or_s0,
adc_data_s1,
adc_or_s1,
adc_data_s2,
adc_or_s2,
adc_data_s3,
adc_or_s3,
// dma interface
adc_valid,
adc_data,
adc_dovf,
// drp interface
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked,
// delay interface
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack,
// status and control signals
mmcm_rst,
adc_rst,
adc_status);
// parameters
parameter PCORE_ID = 0;
// device interface
input adc_clk;
input [11:0] adc_data_s0;
input adc_or_s0;
input [11:0] adc_data_s1;
input adc_or_s1;
input [11:0] adc_data_s2;
input adc_or_s2;
input [11:0] adc_data_s3;
input adc_or_s3;
// dma interface
output adc_valid;
output [63:0] adc_data;
input adc_dovf;
// drp interface
input drp_clk;
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ready;
input drp_locked;
// delay interface
input delay_clk;
output delay_rst;
output delay_sel;
output delay_rwn;
output [ 7:0] delay_addr;
output [ 4:0] delay_wdata;
input [ 4:0] delay_rdata;
input delay_ack_t;
input delay_locked;
// processor interface
input up_clk;
input up_rstn;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
output mmcm_rst;
output adc_rst;
input adc_status;
// internal signals
wire up_status_pn_err_s;
wire up_status_pn_oos_s;
wire up_status_or_s;
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire adc_or_s;
wire [47:0] adc_data_in_s;
wire [ 3:0] adc_pnseq_sel_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// internal assignments
assign adc_or_s = adc_or_s0 & adc_or_s1 & adc_or_s2 & adc_or_s3;
assign adc_data_in_s = {adc_data_s3, adc_data_s2, adc_data_s1, adc_data_s0};
// instantiations
axi_ad9434_pnmon i_pnmon (
.adc_clk(adc_clk),
.adc_data(adc_data_in_s),
.adc_pnseq_sel(adc_pnseq_sel_s),
.adc_pn_err(adc_pn_err_s),
.adc_pn_oos(adc_pn_oos_s));
genvar n;
generate
for (n = 0; n < 4; n = n + 1) begin: g_ad_dfmt
ad_datafmt # (
.DATA_WIDTH(12))
i_datafmt (
.clk(adc_clk),
.valid(1'b1),
.data(adc_data_in_s[n*12+11:n*12]),
.valid_out(adc_valid),
.data_out(adc_data[n*16+15:n*16]),
.dfmt_enable(adc_dfmt_enable_s),
.dfmt_type(adc_dfmt_type_s),
.dfmt_se(adc_dfmt_se_s));
end
endgenerate
up_adc_common #(
.PCORE_ID(PCORE_ID))
i_adc_common(
.mmcm_rst(mmcm_rst),
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_r1_mode(),
.adc_ddr_edgesel(),
.adc_pin_mode(),
.adc_status(adc_status),
.adc_status_ovf(adc_dovf),
.adc_status_unf(1'b0),
.adc_clk_ratio(32'd4),
.up_status_pn_err(up_status_pn_err_s),
.up_status_pn_oos(up_status_pn_oos_s),
.up_status_or(up_status_or_s),
.delay_clk(delay_clk),
.delay_rst(delay_rst),
.delay_sel(delay_sel),
.delay_rwn(delay_rwn),
.delay_addr(delay_addr),
.delay_wdata(delay_wdata),
.delay_rdata(delay_rdata),
.delay_ack_t(delay_ack_t),
.delay_locked(delay_locked),
.drp_clk(drp_clk),
.drp_rst(drp_rst),
.drp_sel(drp_sel),
.drp_wr(drp_wr),
.drp_addr(drp_addr),
.drp_wdata(drp_wdata),
.drp_rdata(drp_rdata),
.drp_ready(drp_ready),
.drp_locked(drp_locked),
.up_usr_chanmax(),
.adc_usr_chanmax(),
.up_adc_gpio_in(),
.up_adc_gpio_out(),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel),
.up_wr(up_wr),
.up_addr(up_addr),
.up_wdata(up_wdata),
.up_rdata(up_rdata),
.up_ack(up_ack));
up_adc_channel #(
.PCORE_ADC_CHID(0))
i_adc_channel(
.adc_clk(adc_clk),
.adc_rst(adc_rst),
.adc_enable(),
.adc_iqcor_enb(),
.adc_dcfilt_enb(),
.adc_dfmt_se(adc_dfmt_se_s),
.adc_dfmt_type(adc_dfmt_type_s),
.adc_dfmt_enable(adc_dfmt_enable_s),
.adc_dcfilt_offset(),
.adc_dcfilt_coeff(),
.adc_iqcor_coeff_1(),
.adc_iqcor_coeff_2(),
.adc_pnseq_sel(adc_pnseq_sel_s),
.adc_data_sel(),
.adc_pn_err(adc_pn_err_s),
.adc_pn_oos(adc_pn_oos_s),
.adc_or(adc_or_s),
.up_adc_pn_err(up_status_pn_err_s),
.up_adc_pn_oos(up_status_pn_oos_s),
.up_adc_or(up_status_or_s),
.up_usr_datatype_be(),
.up_usr_datatype_signed(),
.up_usr_datatype_shift(),
.up_usr_datatype_total_bits(),
.up_usr_datatype_bits(),
.up_usr_decimation_m(),
.up_usr_decimation_n(),
.adc_usr_datatype_be(1'b0),
.adc_usr_datatype_signed(1'b1),
.adc_usr_datatype_shift(8'd0),
.adc_usr_datatype_total_bits(8'd16),
.adc_usr_datatype_bits(8'd16),
.adc_usr_decimation_m(16'd1),
.adc_usr_decimation_n(16'd1),
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_sel(up_sel),
.up_wr(up_wr),
.up_addr(up_addr),
.up_wdata(up_wdata),
.up_rdata(up_rdata),
.up_ack(up_ack));
endmodule

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9434_if (
// device interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_data_s0,
adc_or_s0,
adc_data_s1,
adc_or_s1,
adc_data_s2,
adc_or_s2,
adc_data_s3,
adc_or_s3,
// internl reset and clocks
adc_clk,
adc_rst,
adc_status,
// delay interface (for IDELAY macros)
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked,
// mmcm reset
mmcm_rst,
// drp interface for MMCM
drp_clk,
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ready,
drp_locked);
// parameters
parameter PCORE_DEVTYPE = 0; // 0 - 7Series / 1 - 6Series
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// buffer type based on the target device.
localparam PCORE_BUFTYPE = PCORE_DEVTYPE;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [11:0] adc_data_in_p;
input [11:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output [11:0] adc_data_s0;
output adc_or_s0;
output [11:0] adc_data_s1;
output adc_or_s1;
output [11:0] adc_data_s2;
output adc_or_s2;
output [11:0] adc_data_s3;
output adc_or_s3;
// internal reset and clocks
output adc_clk;
input adc_rst;
output adc_status;
// delay control signals
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// mmcm reset
input mmcm_rst;
// drp interface
input drp_clk;
input drp_rst;
input drp_sel;
input drp_wr;
input [11:0] drp_addr;
input [15:0] drp_wdata;
output [15:0] drp_rdata;
output drp_ready;
output drp_locked;
// output registers
reg [ 4:0] delay_rdata = 'b0;
reg delay_ack_t = 'b0;
reg [47:0] adc_data = 'b0;
reg adc_or = 'b0;
// internal registers
reg [12:0] delay_ld = 'd0;
reg adc_status = 'd0;
reg adc_status_m1 = 'd0;
// internal signals
wire [11:0] adc_data_p_s;
wire [11:0] adc_data_n_s;
wire adc_or_p_s;
wire adc_or_n_s;
wire [ 4:0] delay_rdata_s[12:0];
wire adc_clk_in;
wire adc_div_clk;
genvar l_inst;
// output assignment for adc clock (1:4 of the sampling clock)
assign adc_clk = adc_div_clk;
// delay write interface, each delay element can be individually
// addressed, and a delay value can be directly loaded (no inc/dec stuff)
always @(posedge delay_clk) begin
if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
case (delay_addr)
8'd12 : delay_ld <= 13'h1000;
8'd11 : delay_ld <= 13'h0800;
8'd10 : delay_ld <= 13'h0400;
8'd9 : delay_ld <= 13'h0200;
8'd8 : delay_ld <= 13'h0100;
8'd7 : delay_ld <= 13'h0080;
8'd6 : delay_ld <= 13'h0040;
8'd5 : delay_ld <= 13'h0020;
8'd4 : delay_ld <= 13'h0010;
8'd3 : delay_ld <= 13'h0008;
8'd2 : delay_ld <= 13'h0004;
8'd1 : delay_ld <= 13'h0002;
8'd0 : delay_ld <= 13'h0001;
default : delay_ld <= 13'h0000;
endcase
end else begin
delay_ld <= 13'h000;
end
end
// delay read interface, a delay ack toggle is used to transfer data to the
// processor side- delay locked is independently transferred
always @(posedge delay_clk) begin
case (delay_addr)
8'd12 : delay_rdata <= delay_rdata_s[12];
8'd11 : delay_rdata <= delay_rdata_s[11];
8'd10 : delay_rdata <= delay_rdata_s[10];
8'd9 : delay_rdata <= delay_rdata_s[9];
8'd8 : delay_rdata <= delay_rdata_s[8];
8'd7 : delay_rdata <= delay_rdata_s[7];
8'd6 : delay_rdata <= delay_rdata_s[6];
8'd5 : delay_rdata <= delay_rdata_s[5];
8'd4 : delay_rdata <= delay_rdata_s[4];
8'd3 : delay_rdata <= delay_rdata_s[3];
8'd2 : delay_rdata <= delay_rdata_s[2];
8'd1 : delay_rdata <= delay_rdata_s[1];
8'd0 : delay_rdata <= delay_rdata_s[0];
default: delay_rdata <= 5'd0;
endcase
if (delay_sel == 1'b1) begin
delay_ack_t <= ~delay_ack_t;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk_in),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[l_inst]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[l_inst]),
.delay_locked ());
end
endgenerate
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk_in),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_ld (delay_ld[12]),
.delay_wdata (delay_wdata),
.delay_rdata (delay_rdata_s[12]),
.delay_locked (delay_locked));
// clock input buffers and MMCM
ad_serdes_clk #(
.MMCM_DEVICE_TYPE (PCORE_DEVTYPE),
.MMCM_CLKIN_PERIOD (2),
.MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (8))
i_serdes_clk (
.mmcm_rst (mmcm_rst),
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk_in),
.div_clk (adc_div_clk),
.drp_clk (drp_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ready (drp_ready),
.drp_locked (drp_locked));
// input SERDES for data
ad_serdes_in #(
.DEVICE_TYPE(PCORE_DEVTYPE),
.SERDES(1),
.DATA_WIDTH(12),
.PARALLEL_DATA_WIDTH(4))
i_serdes_data (
.rst(adc_rst),
.clk(adc_clk_in),
.div_clk(adc_div_clk),
.data_s0(adc_data_s0),
.data_s1(adc_data_s1),
.data_s2(adc_data_s2),
.data_s3(adc_data_s3),
.data_s4(),
.data_s5(),
.data_s6(),
.data_s7(),
.data_in_p(adc_data_p_s),
.data_in_n(adc_data_n_s));
// input SERDES for overrange
ad_serdes_in #(
.DEVICE_TYPE(PCORE_DEVTYPE),
.SERDES(1),
.DATA_WIDTH(1),
.PARALLEL_DATA_WIDTH(4))
i_serdes_or (
.rst(adc_rst),
.clk(adc_clk_in),
.div_clk(adc_div_clk),
.data_s0(adc_or_s0),
.data_s1(adc_or_s1),
.data_s2(adc_or_s2),
.data_s3(adc_or_s3),
.data_s4(),
.data_s5(),
.data_s6(),
.data_s7(),
.data_in_p(adc_or_p_s),
.data_in_n(adc_or_n_s));
// adc status: adc is up, if both the MMCM and DELAY blocks are up
always @(posedge adc_div_clk) begin
if(adc_rst == 1'b1) begin
adc_status_m1 <= 1'b0;
adc_status <= 1'b0;
end else begin
adc_status_m1 <= drp_locked & delay_locked;
end
end
endmodule

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library/axi_ad9434/axi_ad9434_ip.tcl Normal file
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9434
adi_ip_files axi_ad9434 [list \
"$ad_hdl_dir/library/common/ad_lvds_in.v" \
"$ad_hdl_dir/library/common/ad_serdes_clk.v" \
"$ad_hdl_dir/library/common/ad_mmcm_drp.v" \
"$ad_hdl_dir/library/common/ad_serdes_in.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_ad9434_if.v" \
"axi_ad9434_pnmon.v" \
"axi_ad9434_core.v" \
"axi_ad9434.v" ]
adi_ip_properties axi_ad9434
ipx::save_core [ipx::current_core]

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library/axi_ad9434/axi_ad9434_pnmon.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_ad9434_pnmon (
// adc interface
adc_clk,
adc_data,
// pn interface
adc_pnseq_sel,
adc_pn_err,
adc_pn_oos
);
// adc interface
input adc_clk;
input [47:0] adc_data;
// pn out sync and error
input [ 3:0] adc_pnseq_sel;
output adc_pn_err;
output adc_pn_oos;
// internal registers
reg [47:0] adc_pn_data_in = 'd0;
reg [47:0] adc_pn_data_pn = 'd0;
// internal signals
wire [47:0] adc_pn_data_pn_s;
// prbs pn9 function
function [47:0] pn9;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[8] ^ din[4];
dout[46] = din[7] ^ din[3];
dout[45] = din[6] ^ din[2];
dout[44] = din[5] ^ din[1];
dout[43] = din[4] ^ din[0];
dout[42] = din[3] ^ din[8] ^ din[4];
dout[41] = din[2] ^ din[7] ^ din[3];
dout[40] = din[1] ^ din[6] ^ din[2];
dout[39] = din[0] ^ din[5] ^ din[1];
dout[38] = din[8] ^ din[0];
dout[37] = din[7] ^ din[8] ^ din[4];
dout[36] = din[6] ^ din[7] ^ din[3];
dout[35] = din[5] ^ din[6] ^ din[2];
dout[34] = din[4] ^ din[5] ^ din[1];
dout[33] = din[3] ^ din[4] ^ din[0];
dout[32] = din[2] ^ din[3] ^ din[8] ^ din[4];
dout[31] = din[1] ^ din[2] ^ din[7] ^ din[3];
dout[30] = din[0] ^ din[1] ^ din[6] ^ din[2];
dout[29] = din[8] ^ din[0] ^ din[4] ^ din[5] ^ din[1];
dout[28] = din[7] ^ din[8] ^ din[3] ^ din[0];
dout[27] = din[6] ^ din[7] ^ din[2] ^ din[8] ^ din[4];
dout[26] = din[5] ^ din[6] ^ din[1] ^ din[7] ^ din[3];
dout[25] = din[4] ^ din[5] ^ din[0] ^ din[6] ^ din[2];
dout[24] = din[3] ^ din[8] ^ din[5] ^ din[1];
dout[23] = din[2] ^ din[4] ^ din[7] ^ din[0];
dout[22] = din[1] ^ din[3] ^ din[6] ^ din[8] ^ din[4];
dout[21] = din[0] ^ din[2] ^ din[5] ^ din[7] ^ din[3];
dout[20] = din[8] ^ din[1] ^ din[6] ^ din[2];
dout[19] = din[7] ^ din[0] ^ din[5] ^ din[1];
dout[18] = din[6] ^ din[8] ^ din[0];
dout[17] = din[5] ^ din[7] ^ din[8] ^ din[4];
dout[16] = din[4] ^ din[6] ^ din[7] ^ din[3];
dout[15] = din[3] ^ din[5] ^ din[6] ^ din[2];
dout[14] = din[2] ^ din[4] ^ din[5] ^ din[1];
dout[13] = din[1] ^ din[3] ^ din[4] ^ din[0];
dout[12] = din[0] ^ din[2] ^ din[3] ^ din[8] ^ din[4];
dout[11] = din[8] ^ din[1] ^ din[2] ^ din[4] ^ din[7] ^ din[3];
dout[10] = din[7] ^ din[0] ^ din[1] ^ din[3] ^ din[6] ^ din[2];
dout[9] = din[6] ^ din[8] ^ din[0] ^ din[2] ^ din[4] ^ din[5] ^ din[1];
dout[8] = din[5] ^ din[7] ^ din[8] ^ din[1] ^ din[3] ^ din[0];
dout[7] = din[6] ^ din[7] ^ din[0] ^ din[2] ^ din[8];
dout[6] = din[5] ^ din[6] ^ din[8] ^ din[1] ^ din[4] ^ din[7];
dout[5] = din[4] ^ din[5] ^ din[7] ^ din[0] ^ din[3] ^ din[6];
dout[4] = din[3] ^ din[6] ^ din[8] ^ din[2] ^ din[5];
dout[3] = din[2] ^ din[4] ^ din[5] ^ din[7] ^ din[1];
dout[2] = din[1] ^ din[4] ^ din[3] ^ din[6] ^ din[0];
dout[1] = din[0] ^ din[3] ^ din[2] ^ din[5] ^ din[8] ^ din[4];
dout[0] = din[8] ^ din[2] ^ din[1] ^ din[7] ^ din[3];
pn9 = dout;
end
endfunction
// prbs pn23 function
function [47:0] pn23;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[22] ^ din[17];
dout[46] = din[21] ^ din[16];
dout[45] = din[20] ^ din[15];
dout[44] = din[19] ^ din[14];
dout[43] = din[18] ^ din[13];
dout[42] = din[17] ^ din[12];
dout[41] = din[16] ^ din[11];
dout[40] = din[15] ^ din[10];
dout[39] = din[14] ^ din[9];
dout[38] = din[13] ^ din[8];
dout[37] = din[12] ^ din[7];
dout[36] = din[11] ^ din[6];
dout[35] = din[10] ^ din[5];
dout[34] = din[9] ^ din[4];
dout[33] = din[8] ^ din[3];
dout[32] = din[7] ^ din[2];
dout[31] = din[6] ^ din[1];
dout[30] = din[5] ^ din[0];
dout[29] = din[4] ^ din[22] ^ din[17];
dout[28] = din[3] ^ din[21] ^ din[16];
dout[27] = din[2] ^ din[20] ^ din[15];
dout[26] = din[1] ^ din[19] ^ din[14];
dout[25] = din[0] ^ din[18] ^ din[13];
dout[24] = din[22] ^ din[12];
dout[23] = din[21] ^ din[11];
dout[22] = din[20] ^ din[10];
dout[21] = din[19] ^ din[9];
dout[20] = din[18] ^ din[8];
dout[19] = din[17] ^ din[7];
dout[18] = din[16] ^ din[6];
dout[17] = din[15] ^ din[5];
dout[16] = din[14] ^ din[4];
dout[15] = din[13] ^ din[3];
dout[14] = din[12] ^ din[2];
dout[13] = din[11] ^ din[1];
dout[12] = din[10] ^ din[0];
dout[11] = din[9] ^ din[22] ^ din[17];
dout[10] = din[8] ^ din[21] ^ din[16];
dout[9] = din[7] ^ din[20] ^ din[15];
dout[8] = din[6] ^ din[19] ^ din[14];
dout[7] = din[5] ^ din[18] ^ din[13];
dout[6] = din[4] ^ din[17] ^ din[12];
dout[5] = din[3] ^ din[16] ^ din[11];
dout[4] = din[2] ^ din[15] ^ din[10];
dout[3] = din[1] ^ din[14] ^ din[9];
dout[2] = din[0] ^ din[13] ^ din[8];
dout[1] = din[22] ^ din[12] ^ din[17] ^ din[7];
dout[0] = din[21] ^ din[11] ^ din[16] ^ din[6];
pn23 = dout;
end
endfunction
// pn sequence selection
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
// TODO: verify if this works
adc_pn_data_in <= adc_data;
if(adc_pnseq_sel == 4'b0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(48)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule

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projects/ad9434_fmc/common/ad9434_bd.tcl Normal file
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# ad9434 interface
set adc_clk_p [create_bd_port -dir I adc_clk_p]
set adc_clk_n [create_bd_port -dir I adc_clk_n]
set adc_data_p [create_bd_port -dir I -from 11 -to 0 adc_data_p]
set adc_data_n [create_bd_port -dir I -from 11 -to 0 adc_data_n]
set adc_or_p [create_bd_port -dir I adc_or_p]
set adc_or_n [create_bd_port -dir I adc_or_n]
# spi interface
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
set spi_csn_o [create_bd_port -dir O spi_csn_o]
set spi_mosi_i [create_bd_port -dir I spi_mosi_i]
set spi_mosi_o [create_bd_port -dir O spi_mosi_o]
set spi_miso_i [create_bd_port -dir I spi_miso_i]
# ad9434
set axi_ad9434 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9434:1.0 axi_ad9434]
# dma for ad9434
set axi_ad9434_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9434_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9434_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9434_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9434_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9434_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9434_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9434_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9434_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9434_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9434_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9434_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9434_dma
# dma interconnect
set axi_ad9434_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9434_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9434_dma_interconnect
# additions to default configuration
set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
# spi connections
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_0]
connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
# ad9434 connections
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9434/delay_clk]
connect_bd_net -net axi_ad9434_clk [get_bd_pins axi_ad9434/adc_clk]
connect_bd_net -net axi_ad9434_clk [get_bd_pins axi_ad9434_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9434_clk_in_p [get_bd_ports adc_clk_p] [get_bd_pins axi_ad9434/adc_clk_in_p]
connect_bd_net -net axi_ad9434_clk_in_n [get_bd_ports adc_clk_n] [get_bd_pins axi_ad9434/adc_clk_in_n]
connect_bd_net -net axi_ad9434_data_in_p [get_bd_ports adc_data_p] [get_bd_pins axi_ad9434/adc_data_in_p]
connect_bd_net -net axi_ad9434_data_in_n [get_bd_ports adc_data_n] [get_bd_pins axi_ad9434/adc_data_in_n]
connect_bd_net -net axi_ad9434_or_in_p [get_bd_ports adc_or_p] [get_bd_pins axi_ad9434/adc_or_in_p]
connect_bd_net -net axi_ad9434_or_in_n [get_bd_ports adc_or_n] [get_bd_pins axi_ad9434/adc_or_in_n]
connect_bd_net -net axi_ad9434_denable [get_bd_pins axi_ad9434/adc_dwr] [get_bd_pins axi_ad9434_dma/fifo_wr_en]
connect_bd_net -net axi_ad9434_data [get_bd_pins axi_ad9434/adc_data] [get_bd_pins axi_ad9434_dma/fifo_wr_din]
connect_bd_net -net axi_ad9434_ovf [get_bd_pins axi_ad9434/adc_dovf] [get_bd_pins axi_ad9434_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9434_dma_irq [get_bd_pins axi_ad9434_dma/irq] [get_bd_pins sys_concat_intc/In2]
# cpu interconnect
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9434/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9434_dma/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9434/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9434_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma/s_axi_aresetn]
# memory inteconnect
set dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
connect_bd_net -net dma_clk $dma_clk_source
connect_bd_intf_net -intf_net axi_ad9434_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9434_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9434_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_ad9434_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9434_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma_interconnect/ACLK] $dma_clk_source
connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma_interconnect/M00_ACLK] $dma_clk_source
connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma_interconnect/S00_ACLK] $dma_clk_source
connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma/m_dest_axi_aclk]
connect_bd_net -net dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9434/s_axi/axi_lite] SEG_data_ad9434_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9434_dma/s_axi/axi_lite] SEG_data_ad9434_dma
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9434_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9434_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// 4 wire
input [ 1:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule

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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/ad9434_bd.tcl

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# ad9434
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_p] ; ## G6 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_n] ; ## G7 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[0]] ; ## D08 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[0]] ; ## D09 FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[1]] ; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[1]] ; ## D12 FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[2]] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[2]] ; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[3]] ; ## G09 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[3]] ; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[4]] ; ## H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[4]] ; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[5]] ; ## G12 FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[5]] ; ## G13 FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[6]] ; ## H13 FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[6]] ; ## H14 FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[7]] ; ## G15 FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[7]] ; ## G16 FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[8]] ; ## H16 FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[8]] ; ## H17 FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[9]] ; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[9]] ; ## D15 FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[10]] ; ## C14 FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[10]] ; ## C15 FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[11]] ; ## D17 FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[11]] ; ## D18 FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_p] ; ## C10 FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_n] ; ## C11 FMC_LPC_LA06_N
# spi
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports spi_csn_clk] ; ## G36 FMC_LPC_LA33_P
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports spi_csn_adc] ; ## G37 FMC_LPC_LA33_N
set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports spi_sclk] ; ## H38 FMC_LPC_LA32_N
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports spi_dio[] ; ## H37 FMC_LPC_LA32_P
# clocks
create_clock -name adc_clk -period 1.66667 [get_ports adc_clk_in_p]
create_clock -name adc_core_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_ad9434/adc_clk]
create_clock -name dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
set_clock_groups -asynchronous -group {adc_clk}
set_clock_groups -asynchronous -group {adc_core_clk}
set_clock_groups -asynchronous -group {dma_clk}

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
set project_name ad9434_fmc_zc706
adi_project_create $project_name
adi_project_files $project_name [list "../common/ad9434_spi.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
adi_project_run $project_name

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
adc_clk_p,
adc_clk_n,
adc_data_p,
adc_data_n,
adc_or_p,
adc_or_n,
spi_csn_clk,
spi_csn_adc,
spi_sclk,
spi_dio);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input adc_clk_p;
input adc_clk_n;
input [11:0] adc_data_p;
input [11:0] adc_data_n;
input adc_or_p;
input adc_or_n;
output spi_csn_clk;
output spi_csn_adc;
output spi_sclk;
inout spi_dio;
// internal signals
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire [ 1:0] spi_csn;
wire spi_miso;
wire spi_mosi;
// instantiations
genvar n;
generate
for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd
IOBUF i_iobuf_gpio_bd (
.I (gpio_o[n]),
.O (gpio_i[n]),
.T (gpio_t[n]),
.IO (gpio_bd[n]));
end
endgenerate
assign spi_csn_adc = spi_csn[0];
assign spi_csn_clk = spi_csn[1];
ad9434_spi i_spi (
.spi_csn(spi_csn),
.spi_clk(spi_sclk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_dio)
);
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.spdif (spdif),
.adc_clk_p(adc_clk_p),
.adc_clk_n(adc_clk_n),
.adc_data_p(adc_data_p),
.adc_data_n(adc_data_n),
.adc_or_p(adc_or_p),
.adc_or_n(adc_or_n),
.spi_clk_i(1'b0),
.spi_clk_o(spi_sclk),
.spi_csn_i(1'b1),
.spi_csn_o(spi_csn),
.spi_mosi_i(spi_miso),
.spi_mosi_o(1'b0),
.spi_miso_i(spi_mosi));
endmodule