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Makefile: Simplify sub-project target generation 

Rewrite the sub-project targets without using $(shell) or $(eval) as they
are not required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-03-23 14:55:42 +01:00 committed by István Csomortáni
parent d5040d87ad
commit 685f2eaf1e
1 changed files with 7 additions and 10 deletions
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17
Makefile
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@ -17,18 +17,15 @@ help:
@echo " make adv7511.zed"
PROJECTS := $(filter-out $(NO_PROJ), $(shell ls projects))
define PROJECT_RULE
$1.$2:
cd projects/$1/$2; $(MAKE)
endef
define APROJECT_RULE
$(foreach archname,$(shell ls projects/$1), $(eval $(call PROJECT_RULE,$1,$(archname))))
endef
$(foreach projname,$(PROJECTS), $(eval $(call APROJECT_RULE,$(projname))))
PROJECTS := $(filter-out $(NO_PROJ), $(notdir $(wildcard projects/*)))
SUBPROJECTS := $(foreach projname,$(PROJECTS), \
$(foreach archname,$(notdir $(wildcard projects/$(projname)/*)), \
$(projname).$(archname)))
.PHONY: lib all clean clean-all $(SUBPROJECTS)
.PHONY: lib all clean clean-all
$(SUBPROJECTS):
$(MAKE) -C projects/$(subst .,/,$@)
lib:
$(MAKE) -C library/ all