From 68a50317e906b6267a558c11f69621a72f49216e Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 26 Jun 2017 15:46:33 +0100 Subject: [PATCH] axi_ad9643: Remove deprecated IP --- library/axi_ad9643/Makefile | 69 ----- library/axi_ad9643/axi_ad9643.v | 356 ----------------------- library/axi_ad9643/axi_ad9643_channel.v | 203 ------------- library/axi_ad9643/axi_ad9643_constr.xdc | 1 - library/axi_ad9643/axi_ad9643_if.v | 214 -------------- library/axi_ad9643/axi_ad9643_ip.tcl | 40 --- library/axi_ad9643/axi_ad9643_pnmon.v | 177 ----------- 7 files changed, 1060 deletions(-) delete mode 100644 library/axi_ad9643/Makefile delete mode 100644 library/axi_ad9643/axi_ad9643.v delete mode 100644 library/axi_ad9643/axi_ad9643_channel.v delete mode 100644 library/axi_ad9643/axi_ad9643_constr.xdc delete mode 100644 library/axi_ad9643/axi_ad9643_if.v delete mode 100644 library/axi_ad9643/axi_ad9643_ip.tcl delete mode 100644 library/axi_ad9643/axi_ad9643_pnmon.v diff --git a/library/axi_ad9643/Makefile b/library/axi_ad9643/Makefile deleted file mode 100644 index 54cf8957d..000000000 --- a/library/axi_ad9643/Makefile +++ /dev/null @@ -1,69 +0,0 @@ -#################################################################################### -#################################################################################### -## Copyright 2011(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### -#################################################################################### - -M_DEPS += ../common/ad_datafmt.v -M_DEPS += ../common/ad_dcfilter.v -M_DEPS += ../common/ad_iqcor.v -M_DEPS += ../common/ad_pnmon.v -M_DEPS += ../common/ad_rst.v -M_DEPS += ../common/up_adc_channel.v -M_DEPS += ../common/up_adc_common.v -M_DEPS += ../common/up_axi.v -M_DEPS += ../common/up_clock_mon.v -M_DEPS += ../common/up_delay_cntrl.v -M_DEPS += ../common/up_xfer_cntrl.v -M_DEPS += ../common/up_xfer_status.v -M_DEPS += ../scripts/adi_env.tcl -M_DEPS += ../scripts/adi_ip.tcl -M_DEPS += ../xilinx/common/ad_lvds_clk.v -M_DEPS += ../xilinx/common/ad_lvds_in.v -M_DEPS += ../xilinx/common/ad_mul.v -M_DEPS += ../xilinx/common/ad_rst_constr.xdc -M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc -M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc -M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc -M_DEPS += axi_ad9643.v -M_DEPS += axi_ad9643_channel.v -M_DEPS += axi_ad9643_constr.xdc -M_DEPS += axi_ad9643_if.v -M_DEPS += axi_ad9643_ip.tcl -M_DEPS += axi_ad9643_pnmon.v - -M_VIVADO := vivado -mode batch -source - -M_FLIST := *.cache -M_FLIST += *.data -M_FLIST += *.xpr -M_FLIST += *.log -M_FLIST += component.xml -M_FLIST += *.jou -M_FLIST += xgui -M_FLIST += *.ip_user_files -M_FLIST += *.srcs -M_FLIST += *.hw -M_FLIST += *.sim -M_FLIST += .Xil - - - -.PHONY: all clean clean-all -all: axi_ad9643.xpr - - -clean:clean-all - - -clean-all: - rm -rf $(M_FLIST) - - -axi_ad9643.xpr: $(M_DEPS) - -rm -rf $(M_FLIST) - $(M_VIVADO) axi_ad9643_ip.tcl >> axi_ad9643_ip.log 2>&1 - -#################################################################################### -#################################################################################### diff --git a/library/axi_ad9643/axi_ad9643.v b/library/axi_ad9643/axi_ad9643.v deleted file mode 100644 index e264346ab..000000000 --- a/library/axi_ad9643/axi_ad9643.v +++ /dev/null @@ -1,356 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module axi_ad9643 #( - - parameter ID = 0, - parameter DEVICE_TYPE = 0, - parameter ADC_DATAPATH_DISABLE = 0, - parameter IO_DELAY_GROUP = "adc_if_delay_group") ( - - // adc interface (clk, data, over-range) - - input adc_clk_in_p, - input adc_clk_in_n, - input [13:0] adc_data_in_p, - input [13:0] adc_data_in_n, - input adc_or_in_p, - input adc_or_in_n, - - // delay interface - - input delay_clk, - - // dma interface - - output adc_clk, - output adc_valid_0, - output adc_enable_0, - output [15:0] adc_data_0, - output adc_valid_1, - output adc_enable_1, - output [15:0] adc_data_1, - input adc_dovf, - input adc_dunf, - input [31:0] up_adc_gpio_in, - output [31:0] up_adc_gpio_out, - output adc_rst, - - // axi interface - - input s_axi_aclk, - input s_axi_aresetn, - input s_axi_awvalid, - input [31:0] s_axi_awaddr, - output s_axi_awready, - input s_axi_wvalid, - input [31:0] s_axi_wdata, - input [ 3:0] s_axi_wstrb, - output s_axi_wready, - output s_axi_bvalid, - output [ 1:0] s_axi_bresp, - input s_axi_bready, - input s_axi_arvalid, - input [31:0] s_axi_araddr, - output s_axi_arready, - output s_axi_rvalid, - output [ 1:0] s_axi_rresp, - output [31:0] s_axi_rdata, - input s_axi_rready, - input [ 2:0] s_axi_awprot, - input [ 2:0] s_axi_arprot); - - - // internal registers - - reg up_status_pn_err = 'd0; - reg up_status_pn_oos = 'd0; - reg up_status_or = 'd0; - reg [31:0] up_rdata = 'd0; - reg up_rack = 'd0; - reg up_wack = 'd0; - - // internal clocks & resets - - wire up_rstn; - wire up_clk; - wire delay_rst; - - // internal signals - - wire [13:0] adc_data_a_s; - wire [13:0] adc_data_b_s; - wire adc_or_a_s; - wire adc_or_b_s; - wire [15:0] adc_dcfilter_data_a_s; - wire [15:0] adc_dcfilter_data_b_s; - wire [15:0] adc_channel_data_a_s; - wire [15:0] adc_channel_data_b_s; - wire [ 1:0] up_status_pn_err_s; - wire [ 1:0] up_status_pn_oos_s; - wire [ 1:0] up_status_or_s; - wire adc_ddr_edgesel_s; - wire adc_pin_mode_s; - wire adc_status_s; - wire [14:0] up_dld_s; - wire [74:0] up_dwdata_s; - wire [74:0] up_drdata_s; - wire delay_locked_s; - wire [31:0] up_rdata_s[0:3]; - wire up_rack_s[0:3]; - wire up_wack_s[0:3]; - wire up_wreq_s; - wire [13:0] up_waddr_s; - wire [31:0] up_wdata_s; - wire up_rreq_s; - wire [13:0] up_raddr_s; - - // signal name changes - - assign up_clk = s_axi_aclk; - assign up_rstn = s_axi_aresetn; - - // dma interface - - assign adc_valid_0 = 1'b1; - assign adc_valid_1 = 1'b1; - - // processor read interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_status_pn_err <= 'd0; - up_status_pn_oos <= 'd0; - up_status_or <= 'd0; - up_rdata <= 'd0; - up_rack <= 'd0; - up_wack <= 'd0; - end else begin - up_status_pn_err <= up_status_pn_err_s[0] | up_status_pn_err_s[1]; - up_status_pn_oos <= up_status_pn_oos_s[0] | up_status_pn_oos_s[1]; - up_status_or <= up_status_or_s[0] | up_status_or_s[1]; - up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; - up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; - up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; - end - end - - // channel - - axi_ad9643_channel #( - .Q_OR_I_N(0), - .CHANNEL_ID(0), - .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) - i_channel_0 ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_data (adc_data_a_s), - .adc_or (adc_or_a_s), - .adc_dcfilter_data_out (adc_dcfilter_data_a_s), - .adc_dcfilter_data_in (adc_dcfilter_data_b_s), - .adc_iqcor_data (adc_data_0), - .adc_enable (adc_enable_0), - .up_adc_pn_err (up_status_pn_err_s[0]), - .up_adc_pn_oos (up_status_pn_oos_s[0]), - .up_adc_or (up_status_or_s[0]), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[0]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[0]), - .up_rack (up_rack_s[0])); - - // channel - - axi_ad9643_channel #( - .Q_OR_I_N(1), - .CHANNEL_ID(1), - .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE)) - i_channel_1 ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_data (adc_data_b_s), - .adc_or (adc_or_b_s), - .adc_dcfilter_data_out (adc_dcfilter_data_b_s), - .adc_dcfilter_data_in (adc_dcfilter_data_a_s), - .adc_iqcor_data (adc_data_1), - .adc_enable (adc_enable_1), - .up_adc_pn_err (up_status_pn_err_s[1]), - .up_adc_pn_oos (up_status_pn_oos_s[1]), - .up_adc_or (up_status_or_s[1]), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[1]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[1]), - .up_rack (up_rack_s[1])); - - // main (device interface) - - axi_ad9643_if #( - .DEVICE_TYPE (DEVICE_TYPE), - .IO_DELAY_GROUP (IO_DELAY_GROUP)) - i_if ( - .adc_clk_in_p (adc_clk_in_p), - .adc_clk_in_n (adc_clk_in_n), - .adc_data_in_p (adc_data_in_p), - .adc_data_in_n (adc_data_in_n), - .adc_or_in_p (adc_or_in_p), - .adc_or_in_n (adc_or_in_n), - .adc_clk (adc_clk), - .adc_data_a (adc_data_a_s), - .adc_data_b (adc_data_b_s), - .adc_or_a (adc_or_a_s), - .adc_or_b (adc_or_b_s), - .adc_status (adc_status_s), - .adc_ddr_edgesel (adc_ddr_edgesel_s), - .adc_pin_mode (adc_pin_mode_s), - .up_clk (up_clk), - .up_dld (up_dld_s), - .up_dwdata (up_dwdata_s), - .up_drdata (up_drdata_s), - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked (delay_locked_s)); - - // common processor control - - up_adc_common #(.ID(ID)) i_up_adc_common ( - .mmcm_rst (), - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_r1_mode (), - .adc_ddr_edgesel (adc_ddr_edgesel_s), - .adc_pin_mode (adc_pin_mode_s), - .adc_status (adc_status_s), - .adc_sync_status (1'd0), - .adc_status_ovf (adc_dovf), - .adc_status_unf (adc_dunf), - .adc_clk_ratio (32'd1), - .adc_start_code (), - .adc_sref_sync (), - .adc_sync (), - .up_adc_ce (), - .up_status_pn_err (up_status_pn_err), - .up_status_pn_oos (up_status_pn_oos), - .up_status_or (up_status_or), - .up_drp_sel (), - .up_drp_wr (), - .up_drp_addr (), - .up_drp_wdata (), - .up_drp_rdata (32'd0), - .up_drp_ready (1'd0), - .up_drp_locked (1'd1), - .up_usr_chanmax_out (), - .up_usr_chanmax_in (8'd0), - .up_adc_gpio_in (up_adc_gpio_in), - .up_adc_gpio_out (up_adc_gpio_out), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[2]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[2]), - .up_rack (up_rack_s[2])); - - // adc delay control - - up_delay_cntrl #(.DATA_WIDTH(15), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked (delay_locked_s), - .up_dld (up_dld_s), - .up_dwdata (up_dwdata_s), - .up_drdata (up_drdata_s), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s[3]), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s[3]), - .up_rack (up_rack_s[3])); - - // up bus interface - - up_axi i_up_axi ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_axi_awvalid (s_axi_awvalid), - .up_axi_awaddr (s_axi_awaddr), - .up_axi_awready (s_axi_awready), - .up_axi_wvalid (s_axi_wvalid), - .up_axi_wdata (s_axi_wdata), - .up_axi_wstrb (s_axi_wstrb), - .up_axi_wready (s_axi_wready), - .up_axi_bvalid (s_axi_bvalid), - .up_axi_bresp (s_axi_bresp), - .up_axi_bready (s_axi_bready), - .up_axi_arvalid (s_axi_arvalid), - .up_axi_araddr (s_axi_araddr), - .up_axi_arready (s_axi_arready), - .up_axi_rvalid (s_axi_rvalid), - .up_axi_rresp (s_axi_rresp), - .up_axi_rdata (s_axi_rdata), - .up_axi_rready (s_axi_rready), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata), - .up_rack (up_rack)); - -endmodule - -// *************************************************************************** -// *************************************************************************** - diff --git a/library/axi_ad9643/axi_ad9643_channel.v b/library/axi_ad9643/axi_ad9643_channel.v deleted file mode 100644 index 0a6bc15f9..000000000 --- a/library/axi_ad9643/axi_ad9643_channel.v +++ /dev/null @@ -1,203 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** -// ADC channel- - -`timescale 1ns/100ps - -module axi_ad9643_channel #( - - parameter Q_OR_I_N = 0, - parameter CHANNEL_ID = 0, - parameter DATAPATH_DISABLE = 0) ( - - // adc interface - - input adc_clk, - input adc_rst, - input [13:0] adc_data, - input adc_or, - - // channel interface - - output [15:0] adc_dcfilter_data_out, - input [15:0] adc_dcfilter_data_in, - output [15:0] adc_iqcor_data, - output adc_enable, - output up_adc_pn_err, - output up_adc_pn_oos, - output up_adc_or, - - // processor interface - - input up_rstn, - input up_clk, - input up_wreq, - input [13:0] up_waddr, - input [31:0] up_wdata, - output up_wack, - input up_rreq, - input [13:0] up_raddr, - output [31:0] up_rdata, - output up_rack); - - - // internal signals - - wire [15:0] adc_dfmt_data_s; - wire [15:0] adc_dcfilter_data_s; - wire adc_iqcor_enb_s; - wire adc_dcfilt_enb_s; - wire adc_dfmt_se_s; - wire adc_dfmt_type_s; - wire adc_dfmt_enable_s; - wire [15:0] adc_dcfilt_offset_s; - wire [15:0] adc_dcfilt_coeff_s; - wire [15:0] adc_iqcor_coeff_1_s; - wire [15:0] adc_iqcor_coeff_2_s; - wire [ 3:0] adc_pnseq_sel_s; - wire adc_pn_err_s; - wire adc_pn_oos_s; - - // iq correction inputs - - axi_ad9643_pnmon i_pnmon ( - .adc_clk (adc_clk), - .adc_data (adc_data), - .adc_pn_oos (adc_pn_oos_s), - .adc_pn_err (adc_pn_err_s), - .adc_pnseq_sel (adc_pnseq_sel_s)); - - generate - if (DATAPATH_DISABLE == 1) begin - assign adc_dfmt_data_s = {2'd0, adc_data}; - end else begin - ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt ( - .clk (adc_clk), - .valid (1'b1), - .data (adc_data), - .valid_out (), - .data_out (adc_dfmt_data_s), - .dfmt_enable (adc_dfmt_enable_s), - .dfmt_type (adc_dfmt_type_s), - .dfmt_se (adc_dfmt_se_s)); - end - endgenerate - - generate - if (DATAPATH_DISABLE == 1) begin - assign adc_dcfilter_data_out = adc_dfmt_data_s; - end else begin - ad_dcfilter i_ad_dcfilter ( - .clk (adc_clk), - .valid (1'b1), - .data (adc_dfmt_data_s), - .valid_out (), - .data_out (adc_dcfilter_data_s), - .dcfilt_enb (adc_dcfilt_enb_s), - .dcfilt_coeff (adc_dcfilt_coeff_s), - .dcfilt_offset (adc_dcfilt_offset_s)); - end - endgenerate - - assign adc_dcfilter_data_out = adc_dcfilter_data_s; - - generate - if (DATAPATH_DISABLE == 1) begin - assign adc_iqcor_data = adc_dcfilter_data_s; - end else begin - ad_iqcor #(.Q_OR_I_N(Q_OR_I_N)) i_ad_iqcor ( - .clk (adc_clk), - .valid (1'b1), - .data_in (adc_dcfilter_data_s), - .data_iq (adc_dcfilter_data_in), - .valid_out (), - .data_out (adc_iqcor_data), - .iqcor_enable (adc_iqcor_enb_s), - .iqcor_coeff_1 (adc_iqcor_coeff_1_s), - .iqcor_coeff_2 (adc_iqcor_coeff_2_s)); - end - endgenerate - - up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel ( - .adc_clk (adc_clk), - .adc_rst (adc_rst), - .adc_enable (adc_enable), - .adc_iqcor_enb (adc_iqcor_enb_s), - .adc_dcfilt_enb (adc_dcfilt_enb_s), - .adc_dfmt_se (adc_dfmt_se_s), - .adc_dfmt_type (adc_dfmt_type_s), - .adc_dfmt_enable (adc_dfmt_enable_s), - .adc_dcfilt_offset (adc_dcfilt_offset_s), - .adc_dcfilt_coeff (adc_dcfilt_coeff_s), - .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), - .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), - .adc_pnseq_sel (adc_pnseq_sel_s), - .adc_data_sel (), - .adc_pn_err (adc_pn_err_s), - .adc_pn_oos (adc_pn_oos_s), - .adc_or (adc_or), - .up_adc_pn_err (up_adc_pn_err), - .up_adc_pn_oos (up_adc_pn_oos), - .up_adc_or (up_adc_or), - .up_usr_datatype_be (), - .up_usr_datatype_signed (), - .up_usr_datatype_shift (), - .up_usr_datatype_total_bits (), - .up_usr_datatype_bits (), - .up_usr_decimation_m (), - .up_usr_decimation_n (), - .adc_usr_datatype_be (1'b0), - .adc_usr_datatype_signed (1'b1), - .adc_usr_datatype_shift (8'd0), - .adc_usr_datatype_total_bits (8'd16), - .adc_usr_datatype_bits (8'd16), - .adc_usr_decimation_m (16'd1), - .adc_usr_decimation_n (16'd1), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata), - .up_rack (up_rack)); - -endmodule - -// *************************************************************************** -// *************************************************************************** - diff --git a/library/axi_ad9643/axi_ad9643_constr.xdc b/library/axi_ad9643/axi_ad9643_constr.xdc deleted file mode 100644 index 8b1378917..000000000 --- a/library/axi_ad9643/axi_ad9643_constr.xdc +++ /dev/null @@ -1 +0,0 @@ - diff --git a/library/axi_ad9643/axi_ad9643_if.v b/library/axi_ad9643/axi_ad9643_if.v deleted file mode 100644 index a903bf2db..000000000 --- a/library/axi_ad9643/axi_ad9643_if.v +++ /dev/null @@ -1,214 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** -// This is the LVDS/DDR interface, note that overrange is independent of data path, -// software will not be able to relate overrange to a specific sample! -// Alternative is to concatenate sample value and or status for data. - -`timescale 1ns/100ps - -module axi_ad9643_if #( - - parameter DEVICE_TYPE = 0, - parameter IO_DELAY_GROUP = "adc_if_delay_group") ( - - // adc interface (clk, data, over-range) - - input adc_clk_in_p, - input adc_clk_in_n, - input [13:0] adc_data_in_p, - input [13:0] adc_data_in_n, - input adc_or_in_p, - input adc_or_in_n, - - // interface outputs - - output adc_clk, - output reg [13:0] adc_data_a, - output reg [13:0] adc_data_b, - output reg adc_or_a, - output reg adc_or_b, - output reg adc_status, - - // processor control signals - - input adc_ddr_edgesel, - input adc_pin_mode, - - // delay control signals - - input up_clk, - input [14:0] up_dld, - input [74:0] up_dwdata, - output [74:0] up_drdata, - input delay_clk, - input delay_rst, - output delay_locked); - - - // internal registers - - reg [13:0] adc_data_p = 'd0; - reg [13:0] adc_data_n = 'd0; - reg [13:0] adc_data_p_d = 'd0; - reg adc_or_p = 'd0; - reg adc_or_n = 'd0; - reg adc_or_p_d = 'd0; - reg [13:0] adc_data_mux_a = 'd0; - reg [13:0] adc_data_mux_b = 'd0; - reg adc_or_mux_a = 'd0; - reg adc_or_mux_b = 'd0; - - // internal signals - - wire [13:0] adc_data_p_s; - wire [13:0] adc_data_n_s; - wire adc_or_p_s; - wire adc_or_n_s; - - genvar l_inst; - - // two data pin modes are supported- - // mux - across clock edges (rising or falling edges), - // mux - within clock edges (lower 7 bits and upper 7 bits) - - always @(posedge adc_clk) begin - adc_status <= 1'b1; - adc_data_p <= adc_data_p_s; - adc_data_n <= adc_data_n_s; - adc_data_p_d <= adc_data_p; - adc_or_p <= adc_or_p_s; - adc_or_n <= adc_or_n_s; - adc_or_p_d <= adc_or_p; - end - - always @(posedge adc_clk) begin - if (adc_ddr_edgesel == 1'b1) begin - adc_data_mux_a <= adc_data_p_d; - adc_data_mux_b <= adc_data_n; - adc_or_mux_a <= adc_or_p_d; - adc_or_mux_b <= adc_or_n; - end else begin - adc_data_mux_a <= adc_data_n; - adc_data_mux_b <= adc_data_p; - adc_or_mux_a <= adc_or_n; - adc_or_mux_b <= adc_or_p; - end - end - - always @(posedge adc_clk) begin - if (adc_pin_mode == 1'b1) begin - adc_data_a <= adc_data_mux_a; - adc_data_b <= adc_data_mux_b; - adc_or_a <= adc_or_mux_a; - adc_or_b <= adc_or_mux_b; - end else begin - adc_data_a <= { adc_data_mux_b[13], adc_data_mux_a[13], - adc_data_mux_b[12], adc_data_mux_a[12], - adc_data_mux_b[11], adc_data_mux_a[11], - adc_data_mux_b[10], adc_data_mux_a[10], - adc_data_mux_b[ 9], adc_data_mux_a[ 9], - adc_data_mux_b[ 8], adc_data_mux_a[ 8], - adc_data_mux_b[ 7], adc_data_mux_a[ 7]}; - adc_data_b <= { adc_data_mux_b[ 6], adc_data_mux_a[ 6], - adc_data_mux_b[ 5], adc_data_mux_a[ 5], - adc_data_mux_b[ 4], adc_data_mux_a[ 4], - adc_data_mux_b[ 3], adc_data_mux_a[ 3], - adc_data_mux_b[ 2], adc_data_mux_a[ 2], - adc_data_mux_b[ 1], adc_data_mux_a[ 1], - adc_data_mux_b[ 0], adc_data_mux_a[ 0]}; - adc_or_a <= adc_or_mux_a; - adc_or_b <= adc_or_mux_b; - end - end - - // data interface - - generate - for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if - ad_lvds_in #( - .DEVICE_TYPE (DEVICE_TYPE), - .IODELAY_CTRL (0), - .IODELAY_GROUP (IO_DELAY_GROUP)) - i_adc_data ( - .rx_clk (adc_clk), - .rx_data_in_p (adc_data_in_p[l_inst]), - .rx_data_in_n (adc_data_in_n[l_inst]), - .rx_data_p (adc_data_p_s[l_inst]), - .rx_data_n (adc_data_n_s[l_inst]), - .up_clk (up_clk), - .up_dld (up_dld[l_inst]), - .up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]), - .up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]), - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked ()); - end - endgenerate - - // over-range interface - - ad_lvds_in #( - .DEVICE_TYPE (DEVICE_TYPE), - .IODELAY_CTRL (1), - .IODELAY_GROUP (IO_DELAY_GROUP)) - i_adc_or ( - .rx_clk (adc_clk), - .rx_data_in_p (adc_or_in_p), - .rx_data_in_n (adc_or_in_n), - .rx_data_p (adc_or_p_s), - .rx_data_n (adc_or_n_s), - .up_clk (up_clk), - .up_dld (up_dld[14]), - .up_dwdata (up_dwdata[74:70]), - .up_drdata (up_drdata[74:70]), - .delay_clk (delay_clk), - .delay_rst (delay_rst), - .delay_locked (delay_locked)); - - // clock - - ad_lvds_clk #( - .DEVICE_TYPE (DEVICE_TYPE)) - i_adc_clk ( - .rst (1'b0), - .locked (), - .clk_in_p (adc_clk_in_p), - .clk_in_n (adc_clk_in_n), - .clk (adc_clk)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/library/axi_ad9643/axi_ad9643_ip.tcl b/library/axi_ad9643/axi_ad9643_ip.tcl deleted file mode 100644 index ce80d421e..000000000 --- a/library/axi_ad9643/axi_ad9643_ip.tcl +++ /dev/null @@ -1,40 +0,0 @@ -# ip - -source ../scripts/adi_env.tcl -source $ad_hdl_dir/library/scripts/adi_ip.tcl - -adi_ip_create axi_ad9643 -adi_ip_files axi_ad9643 [list \ - "$ad_hdl_dir/library/common/ad_rst.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_lvds_clk.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_lvds_in.v" \ - "$ad_hdl_dir/library/common/ad_pnmon.v" \ - "$ad_hdl_dir/library/common/ad_datafmt.v" \ - "$ad_hdl_dir/library/common/ad_dcfilter.v" \ - "$ad_hdl_dir/library/common/ad_iqcor.v" \ - "$ad_hdl_dir/library/common/up_axi.v" \ - "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ - "$ad_hdl_dir/library/common/up_xfer_status.v" \ - "$ad_hdl_dir/library/common/up_clock_mon.v" \ - "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ - "$ad_hdl_dir/library/common/up_adc_common.v" \ - "$ad_hdl_dir/library/common/up_adc_channel.v" \ - "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ - "axi_ad9643_pnmon.v" \ - "axi_ad9643_channel.v" \ - "axi_ad9643_if.v" \ - "axi_ad9643_constr.xdc" \ - "axi_ad9643.v" ] - -adi_ip_properties axi_ad9643 - -set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] -set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] -set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]] - -ipx::save_core [ipx::current_core] - diff --git a/library/axi_ad9643/axi_ad9643_pnmon.v b/library/axi_ad9643/axi_ad9643_pnmon.v deleted file mode 100644 index 0bf87882d..000000000 --- a/library/axi_ad9643/axi_ad9643_pnmon.v +++ /dev/null @@ -1,177 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** -// PN monitors - -`timescale 1ns/100ps - -module axi_ad9643_pnmon ( - - // adc interface - - input adc_clk, - input [13:0] adc_data, - - // pn out of sync and error - - output adc_pn_oos, - output adc_pn_err, - input [ 3:0] adc_pnseq_sel); - - // internal registers - - reg adc_valid_in = 'd0; - reg [27:0] adc_pn_data_in = 'd0; - reg [29:0] adc_pn_data_pn = 'd0; - - // internal signals - - wire [27:0] adc_pn_data_in_s; - wire [29:0] adc_pn_data_pn_s; - - // PN23 function - - function [29:0] pn23; - input [29:0] din; - reg [29:0] dout; - begin - dout[29] = din[22] ^ din[17]; - dout[28] = din[21] ^ din[16]; - dout[27] = din[20] ^ din[15]; - dout[26] = din[19] ^ din[14]; - dout[25] = din[18] ^ din[13]; - dout[24] = din[17] ^ din[12]; - dout[23] = din[16] ^ din[11]; - dout[22] = din[15] ^ din[10]; - dout[21] = din[14] ^ din[ 9]; - dout[20] = din[13] ^ din[ 8]; - dout[19] = din[12] ^ din[ 7]; - dout[18] = din[11] ^ din[ 6]; - dout[17] = din[10] ^ din[ 5]; - dout[16] = din[ 9] ^ din[ 4]; - dout[15] = din[ 8] ^ din[ 3]; - dout[14] = din[ 7] ^ din[ 2]; - dout[13] = din[ 6] ^ din[ 1]; - dout[12] = din[ 5] ^ din[ 0]; - dout[11] = din[ 4] ^ din[22] ^ din[17]; - dout[10] = din[ 3] ^ din[21] ^ din[16]; - dout[ 9] = din[ 2] ^ din[20] ^ din[15]; - dout[ 8] = din[ 1] ^ din[19] ^ din[14]; - dout[ 7] = din[ 0] ^ din[18] ^ din[13]; - dout[ 6] = din[22] ^ din[12]; - dout[ 5] = din[21] ^ din[11]; - dout[ 4] = din[20] ^ din[10]; - dout[ 3] = din[19] ^ din[ 9]; - dout[ 2] = din[18] ^ din[ 8]; - dout[ 1] = din[17] ^ din[ 7]; - dout[ 0] = din[16] ^ din[ 6]; - pn23 = dout; - end - endfunction - - // PN9 function - - function [29:0] pn9; - input [29:0] din; - reg [29:0] dout; - begin - dout[29] = din[ 8] ^ din[ 4]; - dout[28] = din[ 7] ^ din[ 3]; - dout[27] = din[ 6] ^ din[ 2]; - dout[26] = din[ 5] ^ din[ 1]; - dout[25] = din[ 4] ^ din[ 0]; - dout[24] = din[ 3] ^ din[ 8] ^ din[ 4]; - dout[23] = din[ 2] ^ din[ 7] ^ din[ 3]; - dout[22] = din[ 1] ^ din[ 6] ^ din[ 2]; - dout[21] = din[ 0] ^ din[ 5] ^ din[ 1]; - dout[20] = din[ 8] ^ din[ 0]; - dout[19] = din[ 7] ^ din[ 8] ^ din[ 4]; - dout[18] = din[ 6] ^ din[ 7] ^ din[ 3]; - dout[17] = din[ 5] ^ din[ 6] ^ din[ 2]; - dout[16] = din[ 4] ^ din[ 5] ^ din[ 1]; - dout[15] = din[ 3] ^ din[ 4] ^ din[ 0]; - dout[14] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; - dout[13] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; - dout[12] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; - dout[11] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; - dout[10] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; - dout[ 9] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; - dout[ 8] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; - dout[ 7] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; - dout[ 6] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; - dout[ 5] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; - dout[ 4] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; - dout[ 3] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; - dout[ 2] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; - dout[ 1] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; - dout[ 0] = din[ 6] ^ din[ 8] ^ din[ 0]; - pn9 = dout; - end - endfunction - - // pn sequence select - - assign adc_pn_data_in_s = {adc_pn_data_in[13:0], ~adc_data[13], adc_data[12:0]}; - assign adc_pn_data_pn_s = (adc_pn_oos == 1'b0) ? adc_pn_data_pn : - { adc_pn_data_pn[29], adc_pn_data_in[27:14], - adc_pn_data_pn[14], adc_pn_data_in[13: 0]}; - - always @(posedge adc_clk) begin - adc_valid_in <= ~adc_valid_in; - adc_pn_data_in <= adc_pn_data_in_s; - if (adc_valid_in == 1'b1) begin - if (adc_pnseq_sel == 4'd0) begin - adc_pn_data_pn <= pn9(adc_pn_data_pn_s); - end else begin - adc_pn_data_pn <= pn23(adc_pn_data_pn_s); - end - end - end - - // pn oos & pn err - - ad_pnmon #(.DATA_WIDTH(30)) i_pnmon ( - .adc_clk (adc_clk), - .adc_valid_in (adc_valid_in), - .adc_data_in ({ adc_pn_data_pn[29], adc_pn_data_in[27:14], - adc_pn_data_pn[14], adc_pn_data_in[13: 0]}), - .adc_data_pn (adc_pn_data_pn), - .adc_pn_oos (adc_pn_oos), - .adc_pn_err (adc_pn_err)); - -endmodule - -// *************************************************************************** -// *************************************************************************** -