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spi_engine: Add a CDC fifo for the SYNC interface too

main
Istvan Csomortani 2019-01-14 11:08:07 +00:00 committed by István Csomortáni
parent a19f6197cc
commit 68c1f92066
1 changed files with 26 additions and 4 deletions
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30
library/spi_engine/axi_spi_engine/axi_spi_engine.v
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@ -38,6 +38,7 @@
module axi_spi_engine #(
parameter CMD_FIFO_ADDRESS_WIDTH = 4,
parameter SYNC_FIFO_ADDRESS_WIDTH = 4,
parameter SDO_FIFO_ADDRESS_WIDTH = 5,
parameter SDI_FIFO_ADDRESS_WIDTH = 5,
parameter MM_IF_TYPE = 0,
@ -152,6 +153,9 @@ module axi_spi_engine #(
wire sdi_fifo_out_ready;
wire sdi_fifo_out_valid;
wire [7:0] sync_fifo_data;
wire sync_fifo_valid;
reg up_sw_reset = 1'b1;
wire up_sw_resetn = ~up_sw_reset;
@ -326,8 +330,8 @@ module axi_spi_engine #(
sync_id <= 'h00;
sync_id_pending <= 1'b0;
end else begin
if (sync_valid == 1'b1) begin
sync_id <= sync_data;
if (sync_fifo_valid == 1'b1) begin
sync_id <= sync_fifo_data;
sync_id_pending <= 1'b1;
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
sync_id_pending <= 1'b0;
@ -335,8 +339,6 @@ module axi_spi_engine #(
end
end
assign sync_ready = 1'b1;
generate if (ASYNC_SPI_CLK) begin
wire spi_reset;
@ -429,6 +431,26 @@ module axi_spi_engine #(
.m_axis_level(sdi_fifo_level)
);
util_axis_fifo #(
.DATA_WIDTH(8),
.ASYNC_CLK(ASYNC_SPI_CLK),
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
.S_AXIS_REGISTERED(0)
) i_sync_fifo (
.s_axis_aclk(spi_clk),
.s_axis_aresetn(spi_resetn),
.s_axis_ready(sync_ready),
.s_axis_valid(sync_valid),
.s_axis_data(sync_data),
.s_axis_empty(),
.m_axis_aclk(clk),
.m_axis_aresetn(up_sw_resetn),
.m_axis_ready(1'b1),
.m_axis_valid(sync_fifo_valid),
.m_axis_data(sync_fifo_data),
.m_axis_level()
);
assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
assign offload0_cmd_wr_data = up_wdata_s[15:0];