From 68c48d9bd4ffb86fd1c8554aa2e9d6ceef3ca5eb Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Mon, 31 Jul 2017 13:11:23 +0200
Subject: [PATCH] util_axis_fifo: Switch to Verilog-2001 style parameter
 declaration

Verilog-2001 style module parameter declaration is the preferred coding
style for this repository.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 library/util_axis_fifo/address_gray.v           |  6 +++---
 library/util_axis_fifo/address_gray_pipelined.v |  6 +++---
 library/util_axis_fifo/address_sync.v           |  4 +++-
 library/util_axis_fifo/util_axis_fifo.v         | 12 ++++++------
 4 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/library/util_axis_fifo/address_gray.v b/library/util_axis_fifo/address_gray.v
index 58532dba1..57920d36d 100644
--- a/library/util_axis_fifo/address_gray.v
+++ b/library/util_axis_fifo/address_gray.v
@@ -33,7 +33,9 @@
 // ***************************************************************************
 // ***************************************************************************
 
-module fifo_address_gray (
+module fifo_address_gray #(
+  parameter ADDRESS_WIDTH = 4
+) (
   input m_axis_aclk,
   input m_axis_aresetn,
   input m_axis_ready,
@@ -49,8 +51,6 @@ module fifo_address_gray (
   output reg [ADDRESS_WIDTH:0] s_axis_room
 );
 
-parameter ADDRESS_WIDTH = 4;
-
 reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
 reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
 
diff --git a/library/util_axis_fifo/address_gray_pipelined.v b/library/util_axis_fifo/address_gray_pipelined.v
index b8940f2ac..9bd457028 100644
--- a/library/util_axis_fifo/address_gray_pipelined.v
+++ b/library/util_axis_fifo/address_gray_pipelined.v
@@ -33,7 +33,9 @@
 // ***************************************************************************
 // ***************************************************************************
 
-module fifo_address_gray_pipelined (
+module fifo_address_gray_pipelined #(
+  parameter ADDRESS_WIDTH = 4
+) (
   input m_axis_aclk,
   input m_axis_aresetn,
   input m_axis_ready,
@@ -50,8 +52,6 @@ module fifo_address_gray_pipelined (
   output reg [ADDRESS_WIDTH:0] s_axis_room
 );
 
-parameter ADDRESS_WIDTH = 4;
-
 reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
 reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
 wire [ADDRESS_WIDTH:0] _s_axis_raddr;
diff --git a/library/util_axis_fifo/address_sync.v b/library/util_axis_fifo/address_sync.v
index f7312bac3..a38fe6443 100644
--- a/library/util_axis_fifo/address_sync.v
+++ b/library/util_axis_fifo/address_sync.v
@@ -33,7 +33,9 @@
 // ***************************************************************************
 // ***************************************************************************
 
-module fifo_address_sync (
+module fifo_address_sync #(
+  parameter ADDRESS_WIDTH = 4
+) (
   input clk,
   input resetn,
 
diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v
index 76b9b59d4..9bc0d955e 100644
--- a/library/util_axis_fifo/util_axis_fifo.v
+++ b/library/util_axis_fifo/util_axis_fifo.v
@@ -33,7 +33,12 @@
 // ***************************************************************************
 // ***************************************************************************
 
-module util_axis_fifo (
+module util_axis_fifo #(
+  parameter DATA_WIDTH = 64,
+  parameter ASYNC_CLK = 1,
+  parameter ADDRESS_WIDTH = 4,
+  parameter S_AXIS_REGISTERED = 1
+) (
   input m_axis_aclk,
   input m_axis_aresetn,
   input m_axis_ready,
@@ -50,11 +55,6 @@ module util_axis_fifo (
   output [ADDRESS_WIDTH:0] s_axis_room
 );
 
-parameter DATA_WIDTH = 64;
-parameter ASYNC_CLK = 1;
-parameter ADDRESS_WIDTH = 4;
-parameter S_AXIS_REGISTERED = 1;
-
 generate if (ADDRESS_WIDTH == 0) begin
 
 reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;