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axi_dmac: Reset fifo_rd_data without delaying the valid data

main
Istvan Csomortani 2017-11-03 13:41:50 +00:00
parent 960883c789
commit 6900c9979b
1 changed files with 2 additions and 7 deletions
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9
library/axi_dmac/dest_fifo_inf.v
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@ -130,13 +130,8 @@ dmac_data_mover # (
); );
always @(posedge clk) begin always @(posedge clk) begin
if ((resetn == 1'b0) || (data_enabled == 1'b0)) begin if (en)
dout <= {DATA_WIDTH{1'b0}}; dout <= (data_valid) ? dout_s : {DATA_WIDTH{1'b0}};
end else begin
if (data_valid) begin
dout <= dout_s;
end
end
end end
dmac_response_generator # ( dmac_response_generator # (