diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl index 2c1f9d35b..0ae7eba93 100644 --- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl @@ -1,17 +1,9 @@ # # Parameter description: # JESD_MODE : Used link layer encoder mode -# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer -# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer +# 64B66B - 64b66b link layer defined in JESD 204C +# 8B10B - 8b10b link layer defined in JESD 204B # -# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) used in 64B66B mode -# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) used in 64B66B mode -# [RX/TX]_PLL_SEL : Used PLL in the Xilinx PHY used in 64B66B mode -# Encoding is: -# 0 - CPLL -# 1 - QPLL0 -# 2 - QPLL1 -# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode # [RX/TX]_JESD_M : Number of converters per link # [RX/TX]_JESD_L : Number of lanes per link # [RX/TX]_JESD_NP : Number of bits per sample @@ -25,12 +17,10 @@ if {$JESD_MODE == "8B10B"} { set DATAPATH_WIDTH 4 set NP12_DATAPATH_WIDTH 6 set ENCODER_SEL 1 - set ADI_PHY_SEL 1 } else { set DATAPATH_WIDTH 8 set NP12_DATAPATH_WIDTH 12 set ENCODER_SEL 2 - set ADI_PHY_SEL 0 } # These are max values specific to the board @@ -114,16 +104,17 @@ set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$ create_bd_port -dir I rx_device_clk create_bd_port -dir I tx_device_clk -if {$ADI_PHY_SEL == 1} { # common xcvr ad_ip_instance util_adxcvr util_mxfe_xcvr ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV_4_5 5 ad_ip_parameter util_mxfe_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES ad_ip_parameter util_mxfe_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES ad_ip_parameter util_mxfe_xcvr CONFIG.RX_OUT_DIV 1 +ad_ip_parameter util_mxfe_xcvr CONFIG.LINK_MODE $ENCODER_SEL ad_ip_instance axi_adxcvr axi_mxfe_rx_xcvr ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.ID 0 +ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.TX_OR_RX_N 0 ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.QPLL_ENABLE 0 @@ -132,83 +123,12 @@ ad_ip_parameter axi_mxfe_rx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0 ad_ip_instance axi_adxcvr axi_mxfe_tx_xcvr ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.ID 0 +ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.TX_OR_RX_N 1 ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.QPLL_ENABLE 1 ad_ip_parameter axi_mxfe_tx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0 -} else { -for {set i 0} {$i < $MAX_RX_LANES} {incr i} { -create_bd_port -dir I rx_data_${i}_n -create_bd_port -dir I rx_data_${i}_p -} - -for {set i 0} {$i < $MAX_TX_LANES} {incr i} { -create_bd_port -dir O tx_data_${i}_n -create_bd_port -dir O tx_data_${i}_p -} - -create_bd_port -dir I rx_sysref_0 -create_bd_port -dir I tx_sysref_0 - -# unused, keep for port map compatibility with JESD204B -create_bd_port -dir O rx_sync_0 -create_bd_port -dir I tx_sync_0 - -# reset generator -ad_ip_instance proc_sys_reset rx_device_clk_rstgen -ad_connect rx_device_clk rx_device_clk_rstgen/slowest_sync_clk -ad_connect $sys_cpu_resetn rx_device_clk_rstgen/ext_reset_in - -ad_ip_instance proc_sys_reset tx_device_clk_rstgen -ad_connect tx_device_clk tx_device_clk_rstgen/slowest_sync_clk -ad_connect $sys_cpu_resetn tx_device_clk_rstgen/ext_reset_in - -# Common PHYs -# Use two instances since they are located on different SLRS -set rx_rate $ad_project_params(RX_RATE) -set tx_rate $ad_project_params(TX_RATE) -set ref_clk_rate $ad_project_params(REF_CLK_RATE) - -ad_ip_instance jesd204_phy jesd204_phy_121 [list \ - C_LANES {4} \ - GT_Line_Rate $tx_rate \ - GT_REFCLK_FREQ $ref_clk_rate \ - DRPCLK_FREQ {50} \ - C_PLL_SELECTION $ad_project_params(TX_PLL_SEL) \ - RX_GT_Line_Rate $rx_rate \ - RX_GT_REFCLK_FREQ $ref_clk_rate \ - RX_PLL_SELECTION $ad_project_params(RX_PLL_SEL) \ - GT_Location {X0Y8} \ - Tx_JesdVersion {1} \ - Rx_JesdVersion {1} \ - Tx_use_64b {1} \ - Rx_use_64b {1} \ - Min_Line_Rate [expr min($rx_rate,$tx_rate)] \ - Max_Line_Rate [expr max($rx_rate,$tx_rate)] \ - Axi_Lite {true} \ -] - -ad_ip_instance jesd204_phy jesd204_phy_126 [list \ - C_LANES {4} \ - GT_Line_Rate $tx_rate \ - GT_REFCLK_FREQ $ref_clk_rate \ - DRPCLK_FREQ {50} \ - C_PLL_SELECTION $ad_project_params(TX_PLL_SEL) \ - RX_GT_Line_Rate $rx_rate \ - RX_GT_REFCLK_FREQ $ref_clk_rate \ - RX_PLL_SELECTION $ad_project_params(RX_PLL_SEL) \ - GT_Location {X0Y28} \ - Tx_JesdVersion {1} \ - Rx_JesdVersion {1} \ - Tx_use_64b {1} \ - Rx_use_64b {1} \ - Min_Line_Rate [expr min($rx_rate,$tx_rate)] \ - Max_Line_Rate [expr max($rx_rate,$tx_rate)] \ - Axi_Lite {true} \ -] -} - # adc peripherals adi_axi_jesd204_rx_create axi_mxfe_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL @@ -290,7 +210,6 @@ ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width create_bd_port -dir I ref_clk_q0 create_bd_port -dir I ref_clk_q1 -if {$ADI_PHY_SEL == 1} { for {set i 0} {$i < [expr max($TX_NUM_OF_LANES,$RX_NUM_OF_LANES)]} {incr i} { set quad_index [expr int($i / 4)] ad_xcvrpll ref_clk_q$quad_index util_mxfe_xcvr/cpll_ref_clk_$i @@ -311,48 +230,6 @@ ad_xcvrcon util_mxfe_xcvr axi_mxfe_rx_xcvr axi_mxfe_rx_jesd {} {} rx_device_clk # connections (dac) ad_xcvrcon util_mxfe_xcvr axi_mxfe_tx_xcvr axi_mxfe_tx_jesd {} {} tx_device_clk -} else { -ad_connect ref_clk_q0 jesd204_phy_121/cpll_refclk -ad_connect ref_clk_q0 jesd204_phy_121/qpll0_refclk -ad_connect ref_clk_q0 jesd204_phy_121/qpll1_refclk -ad_connect ref_clk_q1 jesd204_phy_126/cpll_refclk -ad_connect ref_clk_q1 jesd204_phy_126/qpll0_refclk -ad_connect ref_clk_q1 jesd204_phy_126/qpll1_refclk - -# link clock domain - -ad_ip_instance util_ds_buf txoutclk_BUFG_GT -ad_ip_parameter txoutclk_BUFG_GT CONFIG.C_BUF_TYPE {BUFG_GT} -ad_connect txoutclk_BUFG_GT/BUFG_GT_CE VCC -ad_connect txoutclk_BUFG_GT/BUFG_GT_CEMASK GND -ad_connect txoutclk_BUFG_GT/BUFG_GT_CLR GND -ad_connect txoutclk_BUFG_GT/BUFG_GT_CLRMASK GND -ad_connect txoutclk_BUFG_GT/BUFG_GT_DIV GND -ad_connect jesd204_phy_121/txoutclk txoutclk_BUFG_GT/BUFG_GT_I - -set tx_link_clock txoutclk_BUFG_GT/BUFG_GT_O - -ad_ip_instance util_ds_buf rxoutclk_BUFG_GT -ad_ip_parameter rxoutclk_BUFG_GT CONFIG.C_BUF_TYPE {BUFG_GT} -ad_connect rxoutclk_BUFG_GT/BUFG_GT_CE VCC -ad_connect rxoutclk_BUFG_GT/BUFG_GT_CEMASK GND -ad_connect rxoutclk_BUFG_GT/BUFG_GT_CLR GND -ad_connect rxoutclk_BUFG_GT/BUFG_GT_CLRMASK GND -ad_connect rxoutclk_BUFG_GT/BUFG_GT_DIV GND -ad_connect jesd204_phy_121/rxoutclk rxoutclk_BUFG_GT/BUFG_GT_I - -set rx_link_clock rxoutclk_BUFG_GT/BUFG_GT_O - -ad_connect $tx_link_clock jesd204_phy_121/tx_core_clk -ad_connect $tx_link_clock jesd204_phy_126/tx_core_clk -ad_connect $tx_link_clock axi_mxfe_tx_jesd/link_clk -ad_connect tx_device_clk axi_mxfe_tx_jesd/device_clk - -ad_connect $rx_link_clock jesd204_phy_121/rx_core_clk -ad_connect $rx_link_clock jesd204_phy_126/rx_core_clk -ad_connect $rx_link_clock axi_mxfe_rx_jesd/link_clk -ad_connect rx_device_clk axi_mxfe_rx_jesd/device_clk -} # device clock domain ad_connect rx_device_clk rx_mxfe_tpl_core/link_clk @@ -379,71 +256,9 @@ ad_connect $sys_cpu_resetn axi_mxfe_rx_dma/m_dest_axi_aresetn ad_connect $sys_dma_resetn axi_mxfe_tx_dma/m_src_axi_aresetn ad_connect $sys_dma_reset mxfe_dac_fifo/dma_rst -if {$ADI_PHY_SEL == 0} { -ad_connect jesd204_phy_121/tx_sys_reset GND -ad_connect jesd204_phy_126/tx_sys_reset GND - -ad_connect jesd204_phy_121/rx_sys_reset GND -ad_connect jesd204_phy_126/rx_sys_reset GND - -ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy_121/tx_reset_gt -ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy_121/rx_reset_gt -ad_connect axi_mxfe_tx_jesd/tx_axi/device_reset jesd204_phy_126/tx_reset_gt -ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy_126/rx_reset_gt -} # # connect adc dataflow # -if {$ADI_PHY_SEL == 0} { -# Rx Physical lanes to PHY -ad_ip_instance xlconcat rx_concat_3_0_p [list NUM_PORTS {4}] -ad_ip_instance xlconcat rx_concat_3_0_n [list NUM_PORTS {4}] - -ad_connect rx_data_0_p rx_concat_3_0_p/In0 -ad_connect rx_data_1_p rx_concat_3_0_p/In1 -ad_connect rx_data_2_p rx_concat_3_0_p/In2 -ad_connect rx_data_3_p rx_concat_3_0_p/In3 - -ad_connect rx_data_0_n rx_concat_3_0_n/In0 -ad_connect rx_data_1_n rx_concat_3_0_n/In1 -ad_connect rx_data_2_n rx_concat_3_0_n/In2 -ad_connect rx_data_3_n rx_concat_3_0_n/In3 - -ad_connect jesd204_phy_121/rxp_in rx_concat_3_0_p/dout -ad_connect jesd204_phy_121/rxn_in rx_concat_3_0_n/dout - -ad_ip_instance xlconcat rx_concat_7_4_p [list NUM_PORTS {4}] -ad_ip_instance xlconcat rx_concat_7_4_n [list NUM_PORTS {4}] - -ad_connect rx_data_4_p rx_concat_7_4_p/In0 -ad_connect rx_data_5_p rx_concat_7_4_p/In1 -ad_connect rx_data_6_p rx_concat_7_4_p/In2 -ad_connect rx_data_7_p rx_concat_7_4_p/In3 - -ad_connect rx_data_4_n rx_concat_7_4_n/In0 -ad_connect rx_data_5_n rx_concat_7_4_n/In1 -ad_connect rx_data_6_n rx_concat_7_4_n/In2 -ad_connect rx_data_7_n rx_concat_7_4_n/In3 - -ad_connect jesd204_phy_126/rxp_in rx_concat_7_4_p/dout -ad_connect jesd204_phy_126/rxn_in rx_concat_7_4_n/dout - -# Connect PHY to Link Layer -set logic_lane(0) jesd204_phy_121/gt0_rx -set logic_lane(1) jesd204_phy_121/gt1_rx -set logic_lane(2) jesd204_phy_121/gt2_rx -set logic_lane(3) jesd204_phy_121/gt3_rx -set logic_lane(4) jesd204_phy_126/gt0_rx -set logic_lane(5) jesd204_phy_126/gt1_rx -set logic_lane(6) jesd204_phy_126/gt2_rx -set logic_lane(7) jesd204_phy_126/gt3_rx -for {set j 0} {$j < $RX_NUM_OF_LANES} {incr j} { - ad_connect axi_mxfe_rx_jesd/rx_phy$j $logic_lane($j) -} - -ad_connect rx_sysref_0 axi_mxfe_rx_jesd/sysref - -} # Connect Link Layer to Transport Layer # ad_connect axi_mxfe_rx_jesd/rx_sof rx_mxfe_tpl_core/link_sof @@ -467,52 +282,6 @@ ad_connect mxfe_adc_fifo/dma_xfer_req axi_mxfe_rx_dma/s_axis_xfer_req # connect dac dataflow # -if {$ADI_PHY_SEL == 0} { -# Tx Physical lanes to PHY -# -for {set i 0} {$i < $MAX_TX_LANES} {incr i} { - ad_ip_instance xlslice txp_out_slice_$i [list \ - DIN_TO [expr $i % 4] \ - DIN_FROM [expr $i % 4] \ - DIN_WIDTH {4} \ - DOUT_WIDTH {1} \ - ] - ad_ip_instance xlslice txn_out_slice_$i [list \ - DIN_TO [expr $i % 4] \ - DIN_FROM [expr $i % 4] \ - DIN_WIDTH {4} \ - DOUT_WIDTH {1} \ - ] -} - -for {set i 0} {$i < 4} {incr i} { - ad_connect jesd204_phy_121/txn_out txn_out_slice_$i/Din - ad_connect jesd204_phy_121/txp_out txp_out_slice_$i/Din - ad_connect jesd204_phy_126/txn_out txn_out_slice_[expr $i+4]/Din - ad_connect jesd204_phy_126/txp_out txp_out_slice_[expr $i+4]/Din -} - -for {set i 0} {$i < $MAX_TX_LANES} {incr i} { - ad_connect txn_out_slice_$i/Dout tx_data_${i}_n - ad_connect txp_out_slice_$i/Dout tx_data_${i}_p -} - -# Tx connect PHY to Link Layer -set logic_lane(0) jesd204_phy_121/gt0_tx -set logic_lane(1) jesd204_phy_121/gt1_tx -set logic_lane(2) jesd204_phy_121/gt2_tx -set logic_lane(3) jesd204_phy_121/gt3_tx -set logic_lane(4) jesd204_phy_126/gt0_tx -set logic_lane(5) jesd204_phy_126/gt1_tx -set logic_lane(6) jesd204_phy_126/gt2_tx -set logic_lane(7) jesd204_phy_126/gt3_tx -for {set j 0} {$j < $TX_NUM_OF_LANES} {incr j} { - ad_connect axi_mxfe_tx_jesd/tx_phy$j $logic_lane($j) -} - -ad_connect tx_sysref_0 axi_mxfe_tx_jesd/sysref - -} # Connect Link Layer to Transport Layer # @@ -540,13 +309,8 @@ create_bd_port -dir I dac_fifo_bypass ad_connect mxfe_dac_fifo/bypass dac_fifo_bypass # interconnect (cpu) -if {$ADI_PHY_SEL == 1} { ad_cpu_interconnect 0x44a60000 axi_mxfe_rx_xcvr ad_cpu_interconnect 0x44b60000 axi_mxfe_tx_xcvr -} else { -ad_cpu_interconnect 0x44a60000 jesd204_phy_121 -ad_cpu_interconnect 0x44b60000 jesd204_phy_126 -} ad_cpu_interconnect 0x44a10000 rx_mxfe_tpl_core ad_cpu_interconnect 0x44b10000 tx_mxfe_tpl_core ad_cpu_interconnect 0x44a90000 axi_mxfe_rx_jesd @@ -556,10 +320,7 @@ ad_cpu_interconnect 0x7c430000 axi_mxfe_tx_dma # interconnect (gt/adc) -if {$ADI_PHY_SEL == 1} { ad_mem_hp0_interconnect $sys_cpu_clk axi_mxfe_rx_xcvr/m_axi -} - ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 ad_mem_hp1_interconnect $sys_cpu_clk axi_mxfe_rx_dma/m_dest_axi ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 @@ -572,7 +333,6 @@ ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq ad_cpu_interrupt ps-11 mb-14 axi_mxfe_rx_jesd/irq ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq -if {$ADI_PHY_SEL == 1} { # Create dummy outputs for unused Tx lanes for {set i $TX_NUM_OF_LANES} {$i < 8} {incr i} { create_bd_port -dir O tx_data_${i}_n @@ -583,4 +343,3 @@ for {set i $RX_NUM_OF_LANES} {$i < 8} {incr i} { create_bd_port -dir I rx_data_${i}_n create_bd_port -dir I rx_data_${i}_p } -}