diff --git a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl index bea514e83..5c55b0e9f 100644 --- a/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl +++ b/library/altera/avl_adxcvr/avl_adxcvr_hw.tcl @@ -21,6 +21,7 @@ ad_ip_parameter FRM_BCNT INTEGER 1 false ad_ip_parameter FRM_SCNT INTEGER 1 false ad_ip_parameter MF_FCNT INTEGER 32 false ad_ip_parameter HD INTEGER 1 false +ad_ip_parameter TX_LANE_MAP STRING "" false set_parameter_property LANE_RATE DISPLAY_UNITS "Mbps" set_parameter_property SYSCLK_FREQUENCY UNITS Megahertz @@ -41,6 +42,7 @@ proc p_avl_adxcvr {} { set m_frm_scnt [get_parameter_value "FRM_SCNT"] set m_mf_fcnt [get_parameter_value "MF_FCNT"] set m_hd [get_parameter_value "HD"] + set m_tx_lane_map [get_parameter_value "TX_LANE_MAP"] set m_pllclk_frequency [expr $m_lane_rate / 2] set m_coreclk_frequency [expr $m_lane_rate / 40] @@ -178,6 +180,8 @@ proc p_avl_adxcvr {} { add_connection alt_ip.csr_bit_reversal alt_xphy.tx_ip_csr_bit_reversal add_connection alt_ip.csr_byte_reversal alt_xphy.tx_ip_csr_byte_reversal + set lane_map [regexp -all -inline {\S+} $m_tx_lane_map] + for {set n 0} {$n < $m_num_of_lanes} {incr n} { add_instance alt_phy_${n} altera_jesd204 @@ -198,30 +202,28 @@ proc p_avl_adxcvr {} { add_connection alt_xphy.tx_phy${n}_analogreset alt_phy_${n}.tx_analogreset add_connection alt_xphy.tx_phy${n}_digitalreset alt_phy_${n}.tx_digitalreset add_connection alt_lane_pll.tx_serial_clk alt_phy_${n}.tx_serial_clk0 - add_interface tx_ip_s_${n} conduit end - set_interface_property tx_ip_s_${n} EXPORT_OF alt_xphy.tx_ip_s_${n} - add_interface tx_ip_d_${n} conduit end - set_interface_property tx_ip_d_${n} EXPORT_OF alt_xphy.tx_ip_d_${n} - add_interface tx_phy_s_${n} conduit end - set_interface_property tx_phy_s_${n} EXPORT_OF alt_xphy.tx_phy_s_${n} - add_interface tx_phy_d_${n} conduit end - set_interface_property tx_phy_d_${n} EXPORT_OF alt_xphy.tx_phy_d_${n} add_connection alt_sys_clk.clk alt_phy_${n}.reconfig_clk add_connection alt_sys_clk.clk_reset alt_phy_${n}.reconfig_reset add_interface phy_reconfig_${n} avalon slave set_interface_property phy_reconfig_${n} EXPORT_OF alt_phy_${n}.reconfig_avmm - add_connection alt_phy_${n}.tx_cal_busy alt_xphy.tx_phy${n}_cal_busy - add_connection alt_phy_${n}.phy_csr_tx_pcfifo_full alt_xphy.tx_phy${n}_pcfifo_full - add_connection alt_phy_${n}.phy_csr_tx_pcfifo_empty alt_xphy.tx_phy${n}_pcfifo_empty - add_connection alt_xphy.tx_phy${n}_pcs_data alt_phy_${n}.jesd204_tx_pcs_data - add_connection alt_xphy.tx_phy${n}_pcs_kchar_data alt_phy_${n}.jesd204_tx_pcs_kchar_data - add_connection alt_xphy.tx_phy${n}_elecidle alt_phy_${n}.phy_tx_elecidle - add_connection alt_xphy.tx_phy${n}_csr_lane_polarity alt_phy_${n}.csr_lane_polarity - add_connection alt_xphy.tx_phy${n}_csr_lane_powerdown alt_phy_${n}.csr_lane_powerdown - add_connection alt_xphy.tx_phy${n}_csr_bit_reversal alt_phy_${n}.csr_bit_reversal - add_connection alt_xphy.tx_phy${n}_csr_byte_reversal alt_phy_${n}.csr_byte_reversal + if {$lane_map != {}} { + set m [lindex $lane_map $n] + } else { + set m $n + } + + add_connection alt_phy_${n}.tx_cal_busy alt_xphy.tx_phy${m}_cal_busy + add_connection alt_phy_${n}.phy_csr_tx_pcfifo_full alt_xphy.tx_phy${m}_pcfifo_full + add_connection alt_phy_${n}.phy_csr_tx_pcfifo_empty alt_xphy.tx_phy${m}_pcfifo_empty + add_connection alt_xphy.tx_phy${m}_pcs_data alt_phy_${n}.jesd204_tx_pcs_data + add_connection alt_xphy.tx_phy${m}_pcs_kchar_data alt_phy_${n}.jesd204_tx_pcs_kchar_data + add_connection alt_xphy.tx_phy${m}_elecidle alt_phy_${n}.phy_tx_elecidle + add_connection alt_xphy.tx_phy${m}_csr_lane_polarity alt_phy_${n}.csr_lane_polarity + add_connection alt_xphy.tx_phy${m}_csr_lane_powerdown alt_phy_${n}.csr_lane_powerdown + add_connection alt_xphy.tx_phy${m}_csr_bit_reversal alt_phy_${n}.csr_bit_reversal + add_connection alt_xphy.tx_phy${m}_csr_byte_reversal alt_phy_${n}.csr_byte_reversal } } diff --git a/library/altera/avl_adxphy/avl_adxphy.v b/library/altera/avl_adxphy/avl_adxphy.v index b83655b96..8a90d63b4 100644 --- a/library/altera/avl_adxphy/avl_adxphy.v +++ b/library/altera/avl_adxphy/avl_adxphy.v @@ -217,47 +217,6 @@ module avl_adxphy #( input tx_ip_bit_reversal, input tx_ip_byte_reversal, - // tx-mux interface - - input [ 2:0] tx_ip_s_0, - output [38:0] tx_ip_d_0, - output [ 2:0] tx_phy_s_0, - input [38:0] tx_phy_d_0, - - input [ 2:0] tx_ip_s_1, - output [38:0] tx_ip_d_1, - output [ 2:0] tx_phy_s_1, - input [38:0] tx_phy_d_1, - - input [ 2:0] tx_ip_s_2, - output [38:0] tx_ip_d_2, - output [ 2:0] tx_phy_s_2, - input [38:0] tx_phy_d_2, - - input [ 2:0] tx_ip_s_3, - output [38:0] tx_ip_d_3, - output [ 2:0] tx_phy_s_3, - input [38:0] tx_phy_d_3, - - input [ 2:0] tx_ip_s_4, - output [38:0] tx_ip_d_4, - output [ 2:0] tx_phy_s_4, - input [38:0] tx_phy_d_4, - - input [ 2:0] tx_ip_s_5, - output [38:0] tx_ip_d_5, - output [ 2:0] tx_phy_s_5, - input [38:0] tx_phy_d_5, - - input [ 2:0] tx_ip_s_6, - output [38:0] tx_ip_d_6, - output [ 2:0] tx_phy_s_6, - input [38:0] tx_phy_d_6, - - input [ 2:0] tx_ip_s_7, - output [38:0] tx_ip_d_7, - output [ 2:0] tx_phy_s_7, - input [38:0] tx_phy_d_7, // tx-phy interface @@ -657,26 +616,26 @@ module avl_adxphy #( generate if (NUM_OF_LANES > 0) begin - assign tx_core_cal_busy[0] = tx_ip_s_0[0]; - assign tx_ip_cal_busy[0] = tx_ip_s_0[0]; - assign tx_ip_full[0] = tx_ip_s_0[1]; - assign tx_ip_empty[0] = tx_ip_s_0[2]; + assign tx_core_cal_busy[0] = tx_phy_cal_busy_0; + assign tx_ip_cal_busy[0] = tx_phy_cal_busy_0; + assign tx_ip_full[0] = tx_phy_full_0; + assign tx_ip_empty[0] = tx_phy_empty_0; end endgenerate generate if (NUM_OF_LANES > 0) begin - assign tx_ip_d_0[31: 0] = tx_ip_data[((32*1)-1):(32*0)]; - assign tx_ip_d_0[35:32] = tx_ip_kchar[((4*1)-1):(4*0)]; - assign tx_ip_d_0[36:36] = tx_ip_elecidle[0]; - assign tx_ip_d_0[37:37] = tx_ip_lane_polarity[0]; - assign tx_ip_d_0[38:38] = tx_ip_lane_powerdown[0]; + assign tx_phy_data_0 = tx_ip_data[((32*1)-1):(32*0)]; + assign tx_phy_kchar_0 = tx_ip_kchar[((4*1)-1):(4*0)]; + assign tx_phy_elecidle_0 = tx_ip_elecidle[0]; + assign tx_phy_lane_polarity_0 = tx_ip_lane_polarity[0]; + assign tx_phy_lane_powerdown_0 = tx_ip_lane_powerdown[0]; end else begin - assign tx_ip_d_0[31: 0] = 32'd0; - assign tx_ip_d_0[35:32] = 4'd0; - assign tx_ip_d_0[36:36] = 1'd0; - assign tx_ip_d_0[37:37] = 1'd0; - assign tx_ip_d_0[38:38] = 1'd0; + assign tx_phy_data_0 = 32'd0; + assign tx_phy_kchar_0 = 4'd0; + assign tx_phy_elecidle_0 = 1'd0; + assign tx_phy_lane_polarity_0 = 1'd0; + assign tx_phy_lane_powerdown_0 = 1'd0; end endgenerate @@ -690,39 +649,31 @@ module avl_adxphy #( end endgenerate - assign tx_phy_s_0[0] = tx_phy_cal_busy_0; - assign tx_phy_s_0[1] = tx_phy_full_0; - assign tx_phy_s_0[2] = tx_phy_empty_0; - assign tx_phy_data_0 = tx_phy_d_0[31:0]; - assign tx_phy_kchar_0 = tx_phy_d_0[35:32]; - assign tx_phy_elecidle_0 = tx_phy_d_0[36]; - assign tx_phy_lane_polarity_0 = tx_phy_d_0[37]; - assign tx_phy_lane_powerdown_0 = tx_phy_d_0[38]; assign tx_phy_bit_reversal_0 = tx_ip_bit_reversal; assign tx_phy_byte_reversal_0 = tx_ip_byte_reversal; generate if (NUM_OF_LANES > 1) begin - assign tx_core_cal_busy[1] = tx_ip_s_1[0]; - assign tx_ip_cal_busy[1] = tx_ip_s_1[0]; - assign tx_ip_full[1] = tx_ip_s_1[1]; - assign tx_ip_empty[1] = tx_ip_s_1[2]; + assign tx_core_cal_busy[1] = tx_phy_cal_busy_1; + assign tx_ip_cal_busy[1] = tx_phy_cal_busy_1; + assign tx_ip_full[1] = tx_phy_full_1; + assign tx_ip_empty[1] = tx_phy_empty_1; end endgenerate generate if (NUM_OF_LANES > 1) begin - assign tx_ip_d_1[31: 0] = tx_ip_data[((32*2)-1):(32*1)]; - assign tx_ip_d_1[35:32] = tx_ip_kchar[((4*2)-1):(4*1)]; - assign tx_ip_d_1[36:36] = tx_ip_elecidle[1]; - assign tx_ip_d_1[37:37] = tx_ip_lane_polarity[1]; - assign tx_ip_d_1[38:38] = tx_ip_lane_powerdown[1]; + assign tx_phy_data_1 = tx_ip_data[((32*2)-1):(32*1)]; + assign tx_phy_kchar_1 = tx_ip_kchar[((4*2)-1):(4*1)]; + assign tx_phy_elecidle_1 = tx_ip_elecidle[1]; + assign tx_phy_lane_polarity_1 = tx_ip_lane_polarity[1]; + assign tx_phy_lane_powerdown_1 = tx_ip_lane_powerdown[1]; end else begin - assign tx_ip_d_1[31: 0] = 32'd0; - assign tx_ip_d_1[35:32] = 4'd0; - assign tx_ip_d_1[36:36] = 1'd0; - assign tx_ip_d_1[37:37] = 1'd0; - assign tx_ip_d_1[38:38] = 1'd0; + assign tx_phy_data_1 = 32'd0; + assign tx_phy_kchar_1 = 4'd0; + assign tx_phy_elecidle_1 = 1'd0; + assign tx_phy_lane_polarity_1 = 1'd0; + assign tx_phy_lane_powerdown_1 = 1'd0; end endgenerate @@ -736,39 +687,31 @@ module avl_adxphy #( end endgenerate - assign tx_phy_s_1[0] = tx_phy_cal_busy_1; - assign tx_phy_s_1[1] = tx_phy_full_1; - assign tx_phy_s_1[2] = tx_phy_empty_1; - assign tx_phy_data_1 = tx_phy_d_1[31:0]; - assign tx_phy_kchar_1 = tx_phy_d_1[35:32]; - assign tx_phy_elecidle_1 = tx_phy_d_1[36]; - assign tx_phy_lane_polarity_1 = tx_phy_d_1[37]; - assign tx_phy_lane_powerdown_1 = tx_phy_d_1[38]; assign tx_phy_bit_reversal_1 = tx_ip_bit_reversal; assign tx_phy_byte_reversal_1 = tx_ip_byte_reversal; generate if (NUM_OF_LANES > 2) begin - assign tx_core_cal_busy[2] = tx_ip_s_2[0]; - assign tx_ip_cal_busy[2] = tx_ip_s_2[0]; - assign tx_ip_full[2] = tx_ip_s_2[1]; - assign tx_ip_empty[2] = tx_ip_s_2[2]; + assign tx_core_cal_busy[2] = tx_phy_cal_busy_2; + assign tx_ip_cal_busy[2] = tx_phy_cal_busy_2; + assign tx_ip_full[2] = tx_phy_full_2; + assign tx_ip_empty[2] = tx_phy_empty_2; end endgenerate generate if (NUM_OF_LANES > 2) begin - assign tx_ip_d_2[31: 0] = tx_ip_data[((32*3)-1):(32*2)]; - assign tx_ip_d_2[35:32] = tx_ip_kchar[((4*3)-1):(4*2)]; - assign tx_ip_d_2[36:36] = tx_ip_elecidle[2]; - assign tx_ip_d_2[37:37] = tx_ip_lane_polarity[2]; - assign tx_ip_d_2[38:38] = tx_ip_lane_powerdown[2]; + assign tx_phy_data_2 = tx_ip_data[((32*3)-1):(32*2)]; + assign tx_phy_kchar_2 = tx_ip_kchar[((4*3)-1):(4*2)]; + assign tx_phy_elecidle_2 = tx_ip_elecidle[2]; + assign tx_phy_lane_polarity_2 = tx_ip_lane_polarity[2]; + assign tx_phy_lane_powerdown_2 = tx_ip_lane_powerdown[2]; end else begin - assign tx_ip_d_2[31: 0] = 32'd0; - assign tx_ip_d_2[35:32] = 4'd0; - assign tx_ip_d_2[36:36] = 1'd0; - assign tx_ip_d_2[37:37] = 1'd0; - assign tx_ip_d_2[38:38] = 1'd0; + assign tx_phy_data_2 = 32'd0; + assign tx_phy_kchar_2 = 4'd0; + assign tx_phy_elecidle_2 = 1'd0; + assign tx_phy_lane_polarity_2 = 1'd0; + assign tx_phy_lane_powerdown_2 = 1'd0; end endgenerate @@ -782,39 +725,31 @@ module avl_adxphy #( end endgenerate - assign tx_phy_s_2[0] = tx_phy_cal_busy_2; - assign tx_phy_s_2[1] = tx_phy_full_2; - assign tx_phy_s_2[2] = tx_phy_empty_2; - assign tx_phy_data_2 = tx_phy_d_2[31:0]; - assign tx_phy_kchar_2 = tx_phy_d_2[35:32]; - assign tx_phy_elecidle_2 = tx_phy_d_2[36]; - assign tx_phy_lane_polarity_2 = tx_phy_d_2[37]; - assign tx_phy_lane_powerdown_2 = tx_phy_d_2[38]; assign tx_phy_bit_reversal_2 = tx_ip_bit_reversal; assign tx_phy_byte_reversal_2 = tx_ip_byte_reversal; generate if (NUM_OF_LANES > 3) begin - assign tx_core_cal_busy[3] = tx_ip_s_3[0]; - assign tx_ip_cal_busy[3] = tx_ip_s_3[0]; - assign tx_ip_full[3] = tx_ip_s_3[1]; - assign tx_ip_empty[3] = tx_ip_s_3[2]; + assign tx_core_cal_busy[3] = tx_phy_cal_busy_3; + assign tx_ip_cal_busy[3] = tx_phy_cal_busy_3; + assign tx_ip_full[3] = tx_phy_full_3; + assign tx_ip_empty[3] = tx_phy_empty_3; end endgenerate generate if (NUM_OF_LANES > 3) begin - assign tx_ip_d_3[31: 0] = tx_ip_data[((32*4)-1):(32*3)]; - assign tx_ip_d_3[35:32] = tx_ip_kchar[((4*4)-1):(4*3)]; - assign tx_ip_d_3[36:36] = tx_ip_elecidle[3]; - assign tx_ip_d_3[37:37] = tx_ip_lane_polarity[3]; - assign tx_ip_d_3[38:38] = tx_ip_lane_powerdown[3]; + assign tx_phy_data_3 = tx_ip_data[((32*4)-1):(32*3)]; + assign tx_phy_kchar_3 = tx_ip_kchar[((4*4)-1):(4*3)]; + assign tx_phy_elecidle_3 = tx_ip_elecidle[3]; + assign tx_phy_lane_polarity_3 = tx_ip_lane_polarity[3]; + assign tx_phy_lane_powerdown_3 = tx_ip_lane_powerdown[3]; end else begin - assign tx_ip_d_3[31: 0] = 32'd0; - assign tx_ip_d_3[35:32] = 4'd0; - assign tx_ip_d_3[36:36] = 1'd0; - assign tx_ip_d_3[37:37] = 1'd0; - assign tx_ip_d_3[38:38] = 1'd0; + assign tx_phy_data_3 = 32'd0; + assign tx_phy_kchar_3 = 4'd0; + assign tx_phy_elecidle_3 = 1'd0; + assign tx_phy_lane_polarity_3 = 1'd0; + assign tx_phy_lane_powerdown_3 = 1'd0; end endgenerate @@ -828,39 +763,31 @@ module avl_adxphy #( end endgenerate - assign tx_phy_s_3[0] = tx_phy_cal_busy_3; - assign tx_phy_s_3[1] = tx_phy_full_3; - assign tx_phy_s_3[2] = tx_phy_empty_3; - assign tx_phy_data_3 = tx_phy_d_3[31:0]; - assign tx_phy_kchar_3 = tx_phy_d_3[35:32]; - assign tx_phy_elecidle_3 = tx_phy_d_3[36]; - assign tx_phy_lane_polarity_3 = tx_phy_d_3[37]; - assign tx_phy_lane_powerdown_3 = tx_phy_d_3[38]; assign tx_phy_bit_reversal_3 = tx_ip_bit_reversal; assign tx_phy_byte_reversal_3 = tx_ip_byte_reversal; generate if (NUM_OF_LANES > 4) begin - assign tx_core_cal_busy[4] = tx_ip_s_4[0]; - assign tx_ip_cal_busy[4] = tx_ip_s_4[0]; - assign tx_ip_full[4] = tx_ip_s_4[1]; - assign tx_ip_empty[4] = tx_ip_s_4[2]; + assign tx_core_cal_busy[4] = tx_phy_cal_busy_4; + assign tx_ip_cal_busy[4] = tx_phy_cal_busy_4; + assign tx_ip_full[4] = tx_phy_full_4; + assign tx_ip_empty[4] = tx_phy_empty_4; end endgenerate generate if (NUM_OF_LANES > 4) begin - assign tx_ip_d_4[31: 0] = tx_ip_data[((32*5)-1):(32*4)]; - assign tx_ip_d_4[35:32] = tx_ip_kchar[((4*5)-1):(4*4)]; - assign tx_ip_d_4[36:36] = tx_ip_elecidle[4]; - assign tx_ip_d_4[37:37] = tx_ip_lane_polarity[4]; - assign tx_ip_d_4[38:38] = tx_ip_lane_powerdown[4]; + assign tx_phy_data_4 = tx_ip_data[((32*5)-1):(32*4)]; + assign tx_phy_kchar_4 = tx_ip_kchar[((4*5)-1):(4*4)]; + assign tx_phy_elecidle_4 = tx_ip_elecidle[4]; + assign tx_phy_lane_polarity_4 = tx_ip_lane_polarity[4]; + assign tx_phy_lane_powerdown_4 = tx_ip_lane_powerdown[4]; end else begin - assign tx_ip_d_4[31: 0] = 32'd0; - assign tx_ip_d_4[35:32] = 4'd0; - assign tx_ip_d_4[36:36] = 1'd0; - assign tx_ip_d_4[37:37] = 1'd0; - assign tx_ip_d_4[38:38] = 1'd0; + assign tx_phy_data_4 = 32'd0; + assign tx_phy_kchar_4 = 4'd0; + assign tx_phy_elecidle_4 = 1'd0; + assign tx_phy_lane_polarity_4 = 1'd0; + assign tx_phy_lane_powerdown_4 = 1'd0; end endgenerate @@ -874,39 +801,31 @@ module avl_adxphy #( end endgenerate - assign tx_phy_s_4[0] = tx_phy_cal_busy_4; - assign tx_phy_s_4[1] = tx_phy_full_4; - assign tx_phy_s_4[2] = tx_phy_empty_4; - assign tx_phy_data_4 = tx_phy_d_4[31:0]; - assign tx_phy_kchar_4 = tx_phy_d_4[35:32]; - assign tx_phy_elecidle_4 = tx_phy_d_4[36]; - assign tx_phy_lane_polarity_4 = tx_phy_d_4[37]; - assign tx_phy_lane_powerdown_4 = tx_phy_d_4[38]; assign tx_phy_bit_reversal_4 = tx_ip_bit_reversal; assign tx_phy_byte_reversal_4 = tx_ip_byte_reversal; generate if (NUM_OF_LANES > 5) begin - assign tx_core_cal_busy[5] = tx_ip_s_5[0]; - assign tx_ip_cal_busy[5] = tx_ip_s_5[0]; - assign tx_ip_full[5] = tx_ip_s_5[1]; - assign tx_ip_empty[5] = tx_ip_s_5[2]; + assign tx_core_cal_busy[5] = tx_phy_cal_busy_5; + assign tx_ip_cal_busy[5] = tx_phy_cal_busy_5; + assign tx_ip_full[5] = tx_phy_full_5; + assign tx_ip_empty[5] = tx_phy_empty_5; end endgenerate generate if (NUM_OF_LANES > 5) begin - assign tx_ip_d_5[31: 0] = tx_ip_data[((32*6)-1):(32*5)]; - assign tx_ip_d_5[35:32] = tx_ip_kchar[((4*6)-1):(4*5)]; - assign tx_ip_d_5[36:36] = tx_ip_elecidle[5]; - assign tx_ip_d_5[37:37] = tx_ip_lane_polarity[5]; - assign tx_ip_d_5[38:38] = tx_ip_lane_powerdown[5]; + assign tx_phy_data_5 = tx_ip_data[((32*6)-1):(32*5)]; + assign tx_phy_kchar_5 = tx_ip_kchar[((4*6)-1):(4*5)]; + assign tx_phy_elecidle_5 = tx_ip_elecidle[5]; + assign tx_phy_lane_polarity_5 = tx_ip_lane_polarity[5]; + assign tx_phy_lane_powerdown_5 = tx_ip_lane_powerdown[5]; end else begin - assign tx_ip_d_5[31: 0] = 32'd0; - assign tx_ip_d_5[35:32] = 4'd0; - assign tx_ip_d_5[36:36] = 1'd0; - assign tx_ip_d_5[37:37] = 1'd0; - assign tx_ip_d_5[38:38] = 1'd0; + assign tx_phy_data_5 = 32'd0; + assign tx_phy_kchar_5 = 4'd0; + assign tx_phy_elecidle_5 = 1'd0; + assign tx_phy_lane_polarity_5 = 1'd0; + assign tx_phy_lane_powerdown_5 = 1'd0; end endgenerate @@ -920,39 +839,31 @@ module avl_adxphy #( end endgenerate - assign tx_phy_s_5[0] = tx_phy_cal_busy_5; - assign tx_phy_s_5[1] = tx_phy_full_5; - assign tx_phy_s_5[2] = tx_phy_empty_5; - assign tx_phy_data_5 = tx_phy_d_5[31:0]; - assign tx_phy_kchar_5 = tx_phy_d_5[35:32]; - assign tx_phy_elecidle_5 = tx_phy_d_5[36]; - assign tx_phy_lane_polarity_5 = tx_phy_d_5[37]; - assign tx_phy_lane_powerdown_5 = tx_phy_d_5[38]; assign tx_phy_bit_reversal_5 = tx_ip_bit_reversal; assign tx_phy_byte_reversal_5 = tx_ip_byte_reversal; generate if (NUM_OF_LANES > 6) begin - assign tx_core_cal_busy[6] = tx_ip_s_6[0]; - assign tx_ip_cal_busy[6] = tx_ip_s_6[0]; - assign tx_ip_full[6] = tx_ip_s_6[1]; - assign tx_ip_empty[6] = tx_ip_s_6[2]; + assign tx_core_cal_busy[6] = tx_phy_cal_busy_6; + assign tx_ip_cal_busy[6] = tx_phy_cal_busy_6; + assign tx_ip_full[6] = tx_phy_full_6; + assign tx_ip_empty[6] = tx_phy_empty_6; end endgenerate generate if (NUM_OF_LANES > 6) begin - assign tx_ip_d_6[31: 0] = tx_ip_data[((32*7)-1):(32*6)]; - assign tx_ip_d_6[35:32] = tx_ip_kchar[((4*7)-1):(4*6)]; - assign tx_ip_d_6[36:36] = tx_ip_elecidle[6]; - assign tx_ip_d_6[37:37] = tx_ip_lane_polarity[6]; - assign tx_ip_d_6[38:38] = tx_ip_lane_powerdown[6]; + assign tx_phy_data_6 = tx_ip_data[((32*7)-1):(32*6)]; + assign tx_phy_kchar_6 = tx_ip_kchar[((4*7)-1):(4*6)]; + assign tx_phy_elecidle_6 = tx_ip_elecidle[6]; + assign tx_phy_lane_polarity_6 = tx_ip_lane_polarity[6]; + assign tx_phy_lane_powerdown_6 = tx_ip_lane_powerdown[6]; end else begin - assign tx_ip_d_6[31: 0] = 32'd0; - assign tx_ip_d_6[35:32] = 4'd0; - assign tx_ip_d_6[36:36] = 1'd0; - assign tx_ip_d_6[37:37] = 1'd0; - assign tx_ip_d_6[38:38] = 1'd0; + assign tx_phy_data_6 = 32'd0; + assign tx_phy_kchar_6 = 4'd0; + assign tx_phy_elecidle_6 = 1'd0; + assign tx_phy_lane_polarity_6 = 1'd0; + assign tx_phy_lane_powerdown_6 = 1'd0; end endgenerate @@ -966,39 +877,31 @@ module avl_adxphy #( end endgenerate - assign tx_phy_s_6[0] = tx_phy_cal_busy_6; - assign tx_phy_s_6[1] = tx_phy_full_6; - assign tx_phy_s_6[2] = tx_phy_empty_6; - assign tx_phy_data_6 = tx_phy_d_6[31:0]; - assign tx_phy_kchar_6 = tx_phy_d_6[35:32]; - assign tx_phy_elecidle_6 = tx_phy_d_6[36]; - assign tx_phy_lane_polarity_6 = tx_phy_d_6[37]; - assign tx_phy_lane_powerdown_6 = tx_phy_d_6[38]; assign tx_phy_bit_reversal_6 = tx_ip_bit_reversal; assign tx_phy_byte_reversal_6 = tx_ip_byte_reversal; generate if (NUM_OF_LANES > 7) begin - assign tx_core_cal_busy[7] = tx_ip_s_7[0]; - assign tx_ip_cal_busy[7] = tx_ip_s_7[0]; - assign tx_ip_full[7] = tx_ip_s_7[1]; - assign tx_ip_empty[7] = tx_ip_s_7[2]; + assign tx_core_cal_busy[7] = tx_phy_cal_busy_7; + assign tx_ip_cal_busy[7] = tx_phy_cal_busy_7; + assign tx_ip_full[7] = tx_phy_full_7; + assign tx_ip_empty[7] = tx_phy_empty_7; end endgenerate generate if (NUM_OF_LANES > 7) begin - assign tx_ip_d_7[31: 0] = tx_ip_data[((32*8)-1):(32*7)]; - assign tx_ip_d_7[35:32] = tx_ip_kchar[((4*8)-1):(4*7)]; - assign tx_ip_d_7[36:36] = tx_ip_elecidle[7]; - assign tx_ip_d_7[37:37] = tx_ip_lane_polarity[7]; - assign tx_ip_d_7[38:38] = tx_ip_lane_powerdown[7]; + assign tx_phy_data_7 = tx_ip_data[((32*8)-1):(32*7)]; + assign tx_phy_kchar_7 = tx_ip_kchar[((4*8)-1):(4*7)]; + assign tx_phy_elecidle_7 = tx_ip_elecidle[7]; + assign tx_phy_lane_polarity_7 = tx_ip_lane_polarity[7]; + assign tx_phy_lane_powerdown_7 = tx_ip_lane_powerdown[7]; end else begin - assign tx_ip_d_7[31: 0] = 32'd0; - assign tx_ip_d_7[35:32] = 4'd0; - assign tx_ip_d_7[36:36] = 1'd0; - assign tx_ip_d_7[37:37] = 1'd0; - assign tx_ip_d_7[38:38] = 1'd0; + assign tx_phy_data_7 = 32'd0; + assign tx_phy_kchar_7 = 4'd0; + assign tx_phy_elecidle_7 = 1'd0; + assign tx_phy_lane_polarity_7 = 1'd0; + assign tx_phy_lane_powerdown_7 = 1'd0; end endgenerate @@ -1012,14 +915,6 @@ module avl_adxphy #( end endgenerate - assign tx_phy_s_7[0] = tx_phy_cal_busy_7; - assign tx_phy_s_7[1] = tx_phy_full_7; - assign tx_phy_s_7[2] = tx_phy_empty_7; - assign tx_phy_data_7 = tx_phy_d_7[31:0]; - assign tx_phy_kchar_7 = tx_phy_d_7[35:32]; - assign tx_phy_elecidle_7 = tx_phy_d_7[36]; - assign tx_phy_lane_polarity_7 = tx_phy_d_7[37]; - assign tx_phy_lane_powerdown_7 = tx_phy_d_7[38]; assign tx_phy_bit_reversal_7 = tx_ip_bit_reversal; assign tx_phy_byte_reversal_7 = tx_ip_byte_reversal; diff --git a/library/altera/avl_adxphy/avl_adxphy_hw.tcl b/library/altera/avl_adxphy/avl_adxphy_hw.tcl index 52279d8c0..663eef1be 100644 --- a/library/altera/avl_adxphy/avl_adxphy_hw.tcl +++ b/library/altera/avl_adxphy/avl_adxphy_hw.tcl @@ -55,11 +55,6 @@ proc p_avl_adxphy {} { for {set n 0} {$n < $m_num_of_lanes} {incr n} { - ad_conduit tx_ip_s_${n} export tx_ip_s_${n} input 3 - ad_conduit tx_ip_d_${n} export tx_ip_d_${n} output 39 - ad_conduit tx_phy_s_${n} export tx_phy_s_${n} output 3 - ad_conduit tx_phy_d_${n} export tx_phy_d_${n} input 39 - ad_conduit tx_phy${n}_cal_busy tx_cal_busy tx_phy_cal_busy_${n} input 1 ad_conduit tx_phy${n}_pcfifo_full export tx_phy_full_${n} input 1 ad_conduit tx_phy${n}_pcfifo_empty export tx_phy_empty_${n} input 1 diff --git a/projects/adrv9371x/common/adrv9371x_qsys.tcl b/projects/adrv9371x/common/adrv9371x_qsys.tcl index a839d44ad..e085ba247 100644 --- a/projects/adrv9371x/common/adrv9371x_qsys.tcl +++ b/projects/adrv9371x/common/adrv9371x_qsys.tcl @@ -13,6 +13,8 @@ set_instance_parameter_value avl_ad9371_tx_xcvr {FRM_BCNT} {2} set_instance_parameter_value avl_ad9371_tx_xcvr {FRM_SCNT} {1} set_instance_parameter_value avl_ad9371_tx_xcvr {MF_FCNT} {32} set_instance_parameter_value avl_ad9371_tx_xcvr {HD} {1} +set_instance_parameter_value avl_ad9144_xcvr {TX_LANE_MAP} {3 0 1 2} + add_connection sys_clk.clk avl_ad9371_tx_xcvr.sys_clk add_connection sys_clk.clk_reset avl_ad9371_tx_xcvr.sys_resetn add_interface tx_ref_clk clock sink @@ -29,14 +31,6 @@ add_interface tx_sysref conduit end set_interface_property tx_sysref EXPORT_OF avl_ad9371_tx_xcvr.sysref add_interface tx_sync conduit end set_interface_property tx_sync EXPORT_OF avl_ad9371_tx_xcvr.sync -add_connection avl_ad9371_tx_xcvr.tx_phy_s_0 avl_ad9371_tx_xcvr.tx_ip_s_3 -add_connection avl_ad9371_tx_xcvr.tx_phy_s_1 avl_ad9371_tx_xcvr.tx_ip_s_0 -add_connection avl_ad9371_tx_xcvr.tx_phy_s_2 avl_ad9371_tx_xcvr.tx_ip_s_1 -add_connection avl_ad9371_tx_xcvr.tx_phy_s_3 avl_ad9371_tx_xcvr.tx_ip_s_2 -add_connection avl_ad9371_tx_xcvr.tx_ip_d_3 avl_ad9371_tx_xcvr.tx_phy_d_0 -add_connection avl_ad9371_tx_xcvr.tx_ip_d_0 avl_ad9371_tx_xcvr.tx_phy_d_1 -add_connection avl_ad9371_tx_xcvr.tx_ip_d_1 avl_ad9371_tx_xcvr.tx_phy_d_2 -add_connection avl_ad9371_tx_xcvr.tx_ip_d_2 avl_ad9371_tx_xcvr.tx_phy_d_3 # ad9371_tx-xcvr diff --git a/projects/daq2/common/daq2_qsys.tcl b/projects/daq2/common/daq2_qsys.tcl index 2a03f211f..63e23b87e 100644 --- a/projects/daq2/common/daq2_qsys.tcl +++ b/projects/daq2/common/daq2_qsys.tcl @@ -13,6 +13,7 @@ set_instance_parameter_value avl_ad9144_xcvr {FRM_BCNT} {1} set_instance_parameter_value avl_ad9144_xcvr {FRM_SCNT} {1} set_instance_parameter_value avl_ad9144_xcvr {MF_FCNT} {32} set_instance_parameter_value avl_ad9144_xcvr {HD} {1} +set_instance_parameter_value avl_ad9144_xcvr {TX_LANE_MAP} {0 3 1 2} add_connection sys_clk.clk avl_ad9144_xcvr.sys_clk add_connection sys_clk.clk_reset avl_ad9144_xcvr.sys_resetn @@ -30,14 +31,6 @@ add_interface tx_sysref conduit end set_interface_property tx_sysref EXPORT_OF avl_ad9144_xcvr.sysref add_interface tx_sync conduit end set_interface_property tx_sync EXPORT_OF avl_ad9144_xcvr.sync -add_connection avl_ad9144_xcvr.tx_phy_s_0 avl_ad9144_xcvr.tx_ip_s_0 -add_connection avl_ad9144_xcvr.tx_phy_s_1 avl_ad9144_xcvr.tx_ip_s_3 -add_connection avl_ad9144_xcvr.tx_phy_s_2 avl_ad9144_xcvr.tx_ip_s_1 -add_connection avl_ad9144_xcvr.tx_phy_s_3 avl_ad9144_xcvr.tx_ip_s_2 -add_connection avl_ad9144_xcvr.tx_ip_d_0 avl_ad9144_xcvr.tx_phy_d_0 -add_connection avl_ad9144_xcvr.tx_ip_d_3 avl_ad9144_xcvr.tx_phy_d_1 -add_connection avl_ad9144_xcvr.tx_ip_d_1 avl_ad9144_xcvr.tx_phy_d_2 -add_connection avl_ad9144_xcvr.tx_ip_d_2 avl_ad9144_xcvr.tx_phy_d_3 # ad9144-xcvr diff --git a/projects/daq3/common/daq3_qsys.tcl b/projects/daq3/common/daq3_qsys.tcl index d627edc7f..164b60f14 100644 --- a/projects/daq3/common/daq3_qsys.tcl +++ b/projects/daq3/common/daq3_qsys.tcl @@ -13,6 +13,7 @@ set_instance_parameter_value avl_ad9152_xcvr {FRM_BCNT} {1} set_instance_parameter_value avl_ad9152_xcvr {FRM_SCNT} {1} set_instance_parameter_value avl_ad9152_xcvr {MF_FCNT} {32} set_instance_parameter_value avl_ad9152_xcvr {HD} {1} +set_instance_parameter_value avl_ad9152_xcvr {TX_LANE_MAP} {0 3 1 2} add_connection sys_clk.clk avl_ad9152_xcvr.sys_clk add_connection sys_clk.clk_reset avl_ad9152_xcvr.sys_resetn @@ -30,14 +31,6 @@ add_interface tx_sysref conduit end set_interface_property tx_sysref EXPORT_OF avl_ad9152_xcvr.sysref add_interface tx_sync conduit end set_interface_property tx_sync EXPORT_OF avl_ad9152_xcvr.sync -add_connection avl_ad9152_xcvr.tx_phy_s_0 avl_ad9152_xcvr.tx_ip_s_0 -add_connection avl_ad9152_xcvr.tx_phy_s_1 avl_ad9152_xcvr.tx_ip_s_3 -add_connection avl_ad9152_xcvr.tx_phy_s_2 avl_ad9152_xcvr.tx_ip_s_1 -add_connection avl_ad9152_xcvr.tx_phy_s_3 avl_ad9152_xcvr.tx_ip_s_2 -add_connection avl_ad9152_xcvr.tx_ip_d_0 avl_ad9152_xcvr.tx_phy_d_0 -add_connection avl_ad9152_xcvr.tx_ip_d_3 avl_ad9152_xcvr.tx_phy_d_1 -add_connection avl_ad9152_xcvr.tx_ip_d_1 avl_ad9152_xcvr.tx_phy_d_2 -add_connection avl_ad9152_xcvr.tx_ip_d_2 avl_ad9152_xcvr.tx_phy_d_3 # ad9152-xcvr