From 69bb9df515bbba8a20fec767aea730114b39d135 Mon Sep 17 00:00:00 2001
From: Laszlo Nagy <laszlo.nagy@analog.com>
Date: Wed, 24 Feb 2021 06:51:17 +0000
Subject: [PATCH] jesd204_rx: Set ASYNC_REG attribute for double syncs

---
 .../jesd204/jesd204_rx/jesd204_rx_constr.ttcl | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl b/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
index 3d8795108..0427a8c43 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
+++ b/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
@@ -61,6 +61,10 @@ set_property IOB <=: $sysref_iob :> \
 
 <: if {$async_clk} { :>
 
+set_property ASYNC_REG TRUE \
+  [get_cells {i_lmfc/cdc_sync_stage1_reg}] \
+  [get_cells {i_lmfc/cdc_sync_stage1_reg}]
+
 set link_clk [get_clocks -of_objects [get_ports -quiet {clk}]]
 set device_clk [get_clocks -of_objects [get_ports -quiet {device_clk}]]
 
@@ -70,17 +74,41 @@ set_false_path \
   -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
     -filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
 
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
+
 # sync event i_sync_lmfc
 set_false_path -quiet \
   -from $device_clk \
   -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
     -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
 
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
+
 set_false_path -quiet \
   -from $link_clk \
   -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
     -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
 
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
+
 # elastic buffer distributed RAM
 set_false_path -quiet \
   -from $link_clk \
@@ -93,6 +121,14 @@ set_false_path \
   -from $device_clk \
   -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
     -filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+   [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
 <: } :>
 
 <: } :>