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jesd204_rx: Set ASYNC_REG attribute for double syncs

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Laszlo Nagy 2021-02-24 06:51:17 +00:00 committed by Laszlo Nagy
parent 8d388dd4f2
commit 69bb9df515
1 changed files with 36 additions and 0 deletions
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36
library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
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@ -61,6 +61,10 @@ set_property IOB <=: $sysref_iob :> \
<: if {$async_clk} { :> <: if {$async_clk} { :>
set_property ASYNC_REG TRUE \
[get_cells {i_lmfc/cdc_sync_stage1_reg}] \
[get_cells {i_lmfc/cdc_sync_stage1_reg}]
set link_clk [get_clocks -of_objects [get_ports -quiet {clk}]] set link_clk [get_clocks -of_objects [get_ports -quiet {clk}]]
set device_clk [get_clocks -of_objects [get_ports -quiet {device_clk}]] set device_clk [get_clocks -of_objects [get_ports -quiet {device_clk}]]
@ -70,17 +74,41 @@ set_false_path \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}] -filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage2_reg* \
-filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}]
# sync event i_sync_lmfc # sync event i_sync_lmfc
set_false_path -quiet \ set_false_path -quiet \
-from $device_clk \ -from $device_clk \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}] -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage2_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}]
set_false_path -quiet \ set_false_path -quiet \
-from $link_clk \ -from $link_clk \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}] -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage2_reg* \
-filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}]
# elastic buffer distributed RAM # elastic buffer distributed RAM
set_false_path -quiet \ set_false_path -quiet \
-from $link_clk \ -from $link_clk \
@ -93,6 +121,14 @@ set_false_path \
-from $device_clk \ -from $device_clk \
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}] -filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage1_reg* \
-filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -quiet -hier *cdc_sync_stage2_reg* \
-filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}]
<: } :> <: } :>
<: } :> <: } :>