fmcomms2/zc706pr- bypass pr as default
Rejeesh Kutty
parent
4739d05269
commit
69ee410d3d
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@ -3,238 +3,119 @@
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create_bd_port -dir O clk
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create_bd_port -dir I dma_dac_i0_enable
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create_bd_port -dir O dma_dac_i0_data
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create_bd_port -dir I dma_dac_i0_valid
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create_bd_port -dir I dma_dac_q0_enable
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create_bd_port -dir O dma_dac_q0_data
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create_bd_port -dir I dma_dac_q0_valid
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create_bd_port -dir I dma_dac_i1_enable
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create_bd_port -dir O dma_dac_i1_data
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create_bd_port -dir I dma_dac_i1_valid
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create_bd_port -dir I dma_dac_q1_enable
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create_bd_port -dir O dma_dac_q1_data
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create_bd_port -dir I dma_dac_q1_valid
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create_bd_port -dir O core_dac_i0_enable
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create_bd_port -dir I core_dac_i0_data
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create_bd_port -dir O core_dac_i0_valid
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create_bd_port -dir O core_dac_q0_enable
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create_bd_port -dir I core_dac_q0_data
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create_bd_port -dir O core_dac_q0_valid
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create_bd_port -dir O core_dac_i1_enable
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create_bd_port -dir I core_dac_i1_data
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create_bd_port -dir O core_dac_i1_valid
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create_bd_port -dir O core_dac_q1_enable
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create_bd_port -dir I core_dac_q1_data
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create_bd_port -dir O core_dac_i0_valid
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create_bd_port -dir O core_dac_q0_valid
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create_bd_port -dir O core_dac_i1_valid
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create_bd_port -dir O core_dac_q1_valid
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create_bd_port -dir I dma_adc_i0_enable
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create_bd_port -dir I dma_adc_i0_data
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create_bd_port -dir I dma_adc_i0_valid
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create_bd_port -dir I dma_adc_q0_enable
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create_bd_port -dir I dma_adc_q0_data
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create_bd_port -dir I dma_adc_q0_valid
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create_bd_port -dir I dma_adc_i1_enable
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create_bd_port -dir I dma_adc_i1_data
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create_bd_port -dir I dma_adc_i1_valid
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create_bd_port -dir I dma_adc_q1_enable
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create_bd_port -dir I dma_adc_q1_data
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create_bd_port -dir I dma_adc_q1_valid
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create_bd_port -dir I -from 15 -to 0 core_dac_i0_data
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create_bd_port -dir I -from 15 -to 0 core_dac_q0_data
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create_bd_port -dir I -from 15 -to 0 core_dac_i1_data
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create_bd_port -dir I -from 15 -to 0 core_dac_q1_data
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create_bd_port -dir I dma_dac_i0_enable
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create_bd_port -dir I dma_dac_q0_enable
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create_bd_port -dir I dma_dac_i1_enable
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create_bd_port -dir I dma_dac_q1_enable
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create_bd_port -dir I dma_dac_i0_valid
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create_bd_port -dir I dma_dac_q0_valid
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create_bd_port -dir I dma_dac_i1_valid
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create_bd_port -dir I dma_dac_q1_valid
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create_bd_port -dir O -from 15 -to 0 dma_dac_i0_data
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create_bd_port -dir O -from 15 -to 0 dma_dac_q0_data
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create_bd_port -dir O -from 15 -to 0 dma_dac_i1_data
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create_bd_port -dir O -from 15 -to 0 dma_dac_q1_data
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create_bd_port -dir O core_adc_i0_enable
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create_bd_port -dir O core_adc_i0_data
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create_bd_port -dir O core_adc_i0_valid
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create_bd_port -dir O core_adc_q0_enable
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create_bd_port -dir O core_adc_q0_data
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create_bd_port -dir O core_adc_q0_valid
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create_bd_port -dir O core_adc_i1_enable
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create_bd_port -dir O core_adc_i1_data
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create_bd_port -dir O core_adc_i1_valid
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create_bd_port -dir O core_adc_q1_enable
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create_bd_port -dir O core_adc_q1_data
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create_bd_port -dir O core_adc_i0_valid
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create_bd_port -dir O core_adc_q0_valid
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create_bd_port -dir O core_adc_i1_valid
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create_bd_port -dir O core_adc_q1_valid
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create_bd_port -dir O -from 15 -to 0 core_adc_i0_data
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create_bd_port -dir O -from 15 -to 0 core_adc_q0_data
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create_bd_port -dir O -from 15 -to 0 core_adc_i1_data
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create_bd_port -dir O -from 15 -to 0 core_adc_q1_data
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create_bd_port -dir I dma_adc_i0_enable
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create_bd_port -dir I dma_adc_q0_enable
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create_bd_port -dir I dma_adc_i1_enable
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create_bd_port -dir I dma_adc_q1_enable
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create_bd_port -dir I dma_adc_i0_valid
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create_bd_port -dir I dma_adc_q0_valid
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create_bd_port -dir I dma_adc_i1_valid
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create_bd_port -dir I dma_adc_q1_valid
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create_bd_port -dir I -from 15 -to 0 dma_adc_i0_data
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create_bd_port -dir I -from 15 -to 0 dma_adc_q0_data
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create_bd_port -dir I -from 15 -to 0 dma_adc_i1_data
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create_bd_port -dir I -from 15 -to 0 dma_adc_q1_data
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create_bd_port -dir I -from 31 -to 0 up_dac_gpio_in
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create_bd_port -dir I -from 31 -to 0 up_adc_gpio_in
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create_bd_port -dir O -from 31 -to 0 up_dac_gpio_out
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create_bd_port -dir O -from 31 -to 0 up_adc_gpio_out
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# re-wiring
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# re-wiring, split between ad9361 core & upack/cpack modules
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_0]] [get_bd_pins util_ad9361_dac_upack/dac_enable_0]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_0]] [get_bd_pins util_ad9361_dac_upack/dac_valid_0]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_0]] [get_bd_pins util_ad9361_dac_upack/dac_data_0]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_1]] [get_bd_pins util_ad9361_dac_upack/dac_enable_1]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_1]] [get_bd_pins util_ad9361_dac_upack/dac_valid_1]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_1]] [get_bd_pins util_ad9361_dac_upack/dac_data_1]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_2]] [get_bd_pins util_ad9361_dac_upack/dac_enable_2]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_2]] [get_bd_pins util_ad9361_dac_upack/dac_valid_2]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_2]] [get_bd_pins util_ad9361_dac_upack/dac_data_2]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_enable_3]] [get_bd_pins util_ad9361_dac_upack/dac_enable_3]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_valid_3]] [get_bd_pins util_ad9361_dac_upack/dac_valid_3]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_dac_upack/dac_data_3]] [get_bd_pins util_ad9361_dac_upack/dac_data_3]
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ad_connect axi_ad9361_clk clk
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_0]] [get_bd_pins util_ad9361_adc_pack/adc_enable_0]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_0]] [get_bd_pins util_ad9361_adc_pack/adc_valid_0]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_0]] [get_bd_pins util_ad9361_adc_pack/adc_data_0]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_1]] [get_bd_pins util_ad9361_adc_pack/adc_enable_1]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_1]] [get_bd_pins util_ad9361_adc_pack/adc_valid_1]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_1]] [get_bd_pins util_ad9361_adc_pack/adc_data_1]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_2]] [get_bd_pins util_ad9361_adc_pack/adc_enable_2]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_2]] [get_bd_pins util_ad9361_adc_pack/adc_valid_2]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_2]] [get_bd_pins util_ad9361_adc_pack/adc_data_2]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_enable_3]] [get_bd_pins util_ad9361_adc_pack/adc_enable_3]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_valid_3]] [get_bd_pins util_ad9361_adc_pack/adc_valid_3]
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disconnect_bd_net [get_bd_nets -of_objects [get_bd_pins util_ad9361_adc_pack/adc_data_3]] [get_bd_pins util_ad9361_adc_pack/adc_data_3]
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ad_reconct util_ad9361_dac_upack/dac_enable_0 dma_dac_i0_enable
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ad_reconct util_ad9361_dac_upack/dac_enable_1 dma_dac_q0_enable
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ad_reconct util_ad9361_dac_upack/dac_enable_2 dma_dac_i1_enable
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ad_reconct util_ad9361_dac_upack/dac_enable_3 dma_dac_q1_enable
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ad_reconct util_ad9361_dac_upack/dac_valid_0 dma_dac_i0_valid
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ad_reconct util_ad9361_dac_upack/dac_valid_1 dma_dac_q0_valid
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ad_reconct util_ad9361_dac_upack/dac_valid_2 dma_dac_i1_valid
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ad_reconct util_ad9361_dac_upack/dac_valid_3 dma_dac_q1_valid
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ad_reconct util_ad9361_dac_upack/dac_data_0 dma_dac_i0_data
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ad_reconct util_ad9361_dac_upack/dac_data_1 dma_dac_q0_data
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ad_reconct util_ad9361_dac_upack/dac_data_2 dma_dac_i1_data
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ad_reconct util_ad9361_dac_upack/dac_data_3 dma_dac_q1_data
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ad_reconct axi_ad9361/dac_enable_i0 core_dac_i0_enable
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ad_reconct axi_ad9361/dac_enable_q0 core_dac_q0_enable
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ad_reconct axi_ad9361/dac_enable_i1 core_dac_i1_enable
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ad_reconct axi_ad9361/dac_enable_q1 core_dac_q1_enable
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ad_reconct axi_ad9361/dac_valid_i0 core_dac_i0_valid
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ad_reconct axi_ad9361/dac_valid_q0 core_dac_q0_valid
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ad_reconct axi_ad9361/dac_valid_i1 core_dac_i1_valid
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ad_reconct axi_ad9361/dac_valid_q1 core_dac_q1_valid
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ad_reconct axi_ad9361/dac_data_i0 core_dac_i0_data
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ad_reconct axi_ad9361/dac_data_q0 core_dac_q0_data
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ad_reconct axi_ad9361/dac_data_i1 core_dac_i1_data
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ad_reconct axi_ad9361/dac_data_q1 core_dac_q1_data
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ad_connect clk axi_ad9361/clk
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ad_reconct util_ad9361_adc_fifo/din_enable_0 dma_adc_i0_enable
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ad_reconct util_ad9361_adc_fifo/din_enable_1 dma_adc_q0_enable
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ad_reconct util_ad9361_adc_fifo/din_enable_2 dma_adc_i1_enable
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ad_reconct util_ad9361_adc_fifo/din_enable_3 dma_adc_q1_enable
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ad_reconct util_ad9361_adc_fifo/din_valid_0 dma_adc_i0_valid
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ad_reconct util_ad9361_adc_fifo/din_valid_1 dma_adc_q0_valid
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ad_reconct util_ad9361_adc_fifo/din_valid_2 dma_adc_i1_valid
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ad_reconct util_ad9361_adc_fifo/din_valid_3 dma_adc_q1_valid
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ad_reconct util_ad9361_adc_fifo/din_data_0 dma_adc_i0_data
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ad_reconct util_ad9361_adc_fifo/din_data_1 dma_adc_q0_data
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ad_reconct util_ad9361_adc_fifo/din_data_2 dma_adc_i1_data
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ad_reconct util_ad9361_adc_fifo/din_data_3 dma_adc_q1_data
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ad_reconct axi_ad9361/adc_enable_i0 core_adc_i0_enable
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ad_reconct axi_ad9361/adc_enable_q0 core_adc_q0_enable
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ad_reconct axi_ad9361/adc_enable_i1 core_adc_i1_enable
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ad_reconct axi_ad9361/adc_enable_q1 core_adc_q1_enable
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ad_reconct axi_ad9361/adc_valid_i0 core_adc_i0_valid
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ad_reconct axi_ad9361/adc_valid_q0 core_adc_q0_valid
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ad_reconct axi_ad9361/adc_valid_i1 core_adc_i1_valid
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ad_reconct axi_ad9361/adc_valid_q1 core_adc_q1_valid
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ad_reconct axi_ad9361/adc_data_i0 core_adc_i0_data
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ad_reconct axi_ad9361/adc_data_q0 core_adc_q0_data
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ad_reconct axi_ad9361/adc_data_i1 core_adc_i1_data
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ad_reconct axi_ad9361/adc_data_q1 core_adc_q1_data
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# tx data path
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ad_connect dma_dac_i0_enable util_ad9361_dac_upack/dac_enable_0
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ad_connect dma_dac_i0_data util_ad9361_dac_upack/dac_data_0
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ad_connect dma_dac_i0_valid util_ad9361_dac_upack/dac_valid_0
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ad_connect dma_dac_q0_enable util_ad9361_dac_upack/dac_enable_1
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ad_connect dma_dac_q0_data util_ad9361_dac_upack/dac_data_1
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ad_connect dma_dac_q0_valid util_ad9361_dac_upack/dac_valid_1
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ad_connect dma_dac_i1_enable util_ad9361_dac_upack/dac_enable_2
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ad_connect dma_dac_i1_data util_ad9361_dac_upack/dac_data_2
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ad_connect dma_dac_i1_valid util_ad9361_dac_upack/dac_valid_2
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ad_connect dma_dac_q1_enable util_ad9361_dac_upack/dac_enable_3
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ad_connect dma_dac_q1_data util_ad9361_dac_upack/dac_data_3
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ad_connect dma_dac_q1_valid util_ad9361_dac_upack/dac_valid_3
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ad_connect core_dac_i0_enable axi_ad9361/dac_enable_i0
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ad_connect core_dac_i0_data axi_ad9361/dac_data_i0
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ad_connect core_dac_i0_valid axi_ad9361/dac_valid_i0
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ad_connect core_dac_q0_enable axi_ad9361/dac_enable_q0
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ad_connect core_dac_q0_data axi_ad9361/dac_data_q0
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ad_connect core_dac_q0_valid axi_ad9361/dac_valid_q0
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ad_connect core_dac_i1_enable axi_ad9361/dac_enable_i1
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ad_connect core_dac_i1_data axi_ad9361/dac_data_i1
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ad_connect core_dac_i1_valid axi_ad9361/dac_valid_i1
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ad_connect core_dac_q1_enable axi_ad9361/dac_enable_q1
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ad_connect core_dac_q1_data axi_ad9361/dac_data_q1
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ad_connect core_dac_q1_valid axi_ad9361/dac_valid_q1
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# rx data path
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ad_connect dma_adc_i0_enable util_ad9361_adc_pack/adc_enable_0
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ad_connect dma_adc_i0_data util_ad9361_adc_pack/adc_data_0
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ad_connect dma_adc_i0_valid util_ad9361_adc_pack/adc_valid_0
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ad_connect dma_adc_q0_enable util_ad9361_adc_pack/adc_enable_1
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ad_connect dma_adc_q0_data util_ad9361_adc_pack/adc_data_1
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ad_connect dma_adc_q0_valid util_ad9361_adc_pack/adc_valid_1
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ad_connect dma_adc_i1_enable util_ad9361_adc_pack/adc_enable_2
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ad_connect dma_adc_i1_data util_ad9361_adc_pack/adc_data_2
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ad_connect dma_adc_i1_valid util_ad9361_adc_pack/adc_valid_2
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ad_connect dma_adc_q1_enable util_ad9361_adc_pack/adc_enable_3
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ad_connect dma_adc_q1_data util_ad9361_adc_pack/adc_data_3
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ad_connect dma_adc_q1_valid util_ad9361_adc_pack/adc_valid_3
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ad_connect core_adc_i0_enable util_ad9361_adc_fifo/dout_enable_0
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ad_connect core_adc_i0_data util_ad9361_adc_fifo/dout_data_0
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ad_connect core_adc_i0_valid util_ad9361_adc_fifo/dout_valid_0
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ad_connect core_adc_q0_enable util_ad9361_adc_fifo/dout_enable_1
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ad_connect core_adc_q0_data util_ad9361_adc_fifo/dout_data_1
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ad_connect core_adc_q0_valid util_ad9361_adc_fifo/dout_valid_1
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ad_connect core_adc_i1_enable util_ad9361_adc_fifo/dout_enable_2
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ad_connect core_adc_i1_data util_ad9361_adc_fifo/dout_data_2
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ad_connect core_adc_i1_valid util_ad9361_adc_fifo/dout_valid_2
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ad_connect core_adc_q1_enable util_ad9361_adc_fifo/dout_enable_3
|
||||
ad_connect core_adc_q1_data util_ad9361_adc_fifo/dout_data_3
|
||||
ad_connect core_adc_q1_valid util_ad9361_adc_fifo/dout_valid_3
|
||||
|
||||
ad_connect up_dac_gpio_in axi_ad9361/up_dac_gpio_in
|
||||
ad_connect up_adc_gpio_in axi_ad9361/up_adc_gpio_in
|
||||
ad_connect up_dac_gpio_out axi_ad9361/up_dac_gpio_out
|
||||
ad_connect up_adc_gpio_out axi_ad9361/up_adc_gpio_out
|
||||
|
||||
# rx side monitoring
|
||||
|
||||
set ila_rx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_0]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_0
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_0
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_0
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_0
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_0
|
||||
|
||||
ad_connect sys_cpu_clk ila_rx_0/clk
|
||||
ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_0/probe0
|
||||
ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_0/probe1
|
||||
|
||||
set ila_rx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_rx_1]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_1
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_1
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_1
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_1
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_1
|
||||
|
||||
ad_connect sys_cpu_clk ila_rx_1/clk
|
||||
ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_1/probe0
|
||||
ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_1/probe1
|
||||
|
||||
set ila_rx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_2]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_2
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_2
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_2
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_2
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_2
|
||||
|
||||
ad_connect sys_cpu_clk ila_rx_2/clk
|
||||
ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_2/probe0
|
||||
ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_2/probe1
|
||||
|
||||
set ila_rx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_rx_3]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_rx_3
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_rx_3
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_rx_3
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_rx_3
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_rx_3
|
||||
|
||||
ad_connect sys_cpu_clk ila_rx_3/clk
|
||||
ad_connect util_ad9361_adc_pack/adc_valid_0 ila_rx_3/probe0
|
||||
ad_connect util_ad9361_adc_pack/adc_data_0 ila_rx_3/probe1
|
||||
|
||||
# rx side monitoring
|
||||
|
||||
set ila_tx_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.1 ila_tx_0]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_0
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_0
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_0
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_0
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_0
|
||||
|
||||
ad_connect axi_ad9361/l_clk ila_tx_0/clk
|
||||
ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_tx_0/probe0
|
||||
ad_connect util_ad9361_adc_fifo/dout_data_0 ila_tx_0/probe1
|
||||
|
||||
set ila_tx_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_1]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_1
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_1
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_1
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_1
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_1
|
||||
|
||||
ad_connect axi_ad9361/l_clk ila_tx_1/clk
|
||||
ad_connect util_ad9361_adc_fifo/dout_valid_1 ila_tx_1/probe0
|
||||
ad_connect util_ad9361_adc_fifo/dout_data_1 ila_tx_1/probe1
|
||||
|
||||
set ila_tx_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_2]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_2
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_2
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_2
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_2
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_2
|
||||
|
||||
ad_connect axi_ad9361/l_clk ila_tx_2/clk
|
||||
ad_connect util_ad9361_adc_fifo/dout_valid_2 ila_tx_2/probe0
|
||||
ad_connect util_ad9361_adc_fifo/dout_data_2 ila_tx_2/probe1
|
||||
|
||||
set ila_tx_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.0 ila_tx_3]
|
||||
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tx_3
|
||||
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_tx_3
|
||||
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tx_3
|
||||
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_tx_3
|
||||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tx_3
|
||||
|
||||
ad_connect axi_ad9361/l_clk ila_tx_3/clk
|
||||
ad_connect util_ad9361_adc_fifo/dout_valid_3 ila_tx_3/probe0
|
||||
ad_connect util_ad9361_adc_fifo/dout_data_3 ila_tx_3/probe1
|
||||
ad_reconct axi_ad9361/up_dac_gpio_in up_dac_gpio_in
|
||||
ad_reconct axi_ad9361/up_adc_gpio_in up_adc_gpio_in
|
||||
ad_reconct axi_ad9361/up_dac_gpio_out up_dac_gpio_out
|
||||
ad_reconct axi_ad9361/up_adc_gpio_out up_adc_gpio_out
|
||||
|
||||
|
|
|
|||
|
|
@ -5,22 +5,30 @@
|
|||
####################################################################################
|
||||
####################################################################################
|
||||
|
||||
M_DEPS := system_project.tcl
|
||||
M_DEPS += ../../scripts/adi_env.tcl
|
||||
M_DEPS += ../../scripts/adi_project.tcl
|
||||
M_DEPS += ../../scripts/adi_board.tcl
|
||||
M_DEPS += system_top.v
|
||||
M_DEPS += system_project.tcl
|
||||
M_DEPS += system_constr.xdc
|
||||
M_DEPS += system_bd.tcl
|
||||
M_DEPS += ../zc706/system_bd.tcl
|
||||
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
|
||||
M_DEPS += ../common/fmcomms2_bd.tcl
|
||||
M_DEPS += ../../scripts/adi_project.tcl
|
||||
M_DEPS += ../../scripts/adi_env.tcl
|
||||
M_DEPS += ../../scripts/adi_board.tcl
|
||||
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
|
||||
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
|
||||
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
|
||||
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
|
||||
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
|
||||
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
|
||||
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
|
||||
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
|
||||
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
|
||||
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
|
||||
M_DEPS += ../../../library/util_upack/util_upack.xpr
|
||||
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
|
||||
M_DEPS += ../zc706/system_bd.tcl
|
||||
M_DEPS += ../zc706/system_constr.xdc
|
||||
M_DEPS += ../common/prcfg_bd.tcl
|
||||
M_DEPS += ../common/prcfg_bb.v
|
||||
|
||||
M_VIVADO := vivado -mode batch -source
|
||||
|
||||
|
|
@ -33,12 +41,15 @@ M_FLIST += xgui
|
|||
M_FLIST += *.runs
|
||||
M_FLIST += *.srcs
|
||||
M_FLIST += *.sdk
|
||||
M_FLIST += *.hw
|
||||
M_FLIST += *.sim
|
||||
M_FLIST += .Xil
|
||||
M_FLIST += *.ip_user_files
|
||||
|
||||
|
||||
|
||||
.PHONY: all lib clean clean-all
|
||||
all: lib fmcomms2_zc706pr.sdk/system_top.hdf
|
||||
all: lib fmcomms2_zc706.sdk/system_top.hdf
|
||||
|
||||
|
||||
clean:
|
||||
|
|
@ -52,13 +63,14 @@ clean-all:clean
|
|||
make -C ../../../library/axi_hdmi_tx clean
|
||||
make -C ../../../library/axi_spdif_tx clean
|
||||
make -C ../../../library/util_cpack clean
|
||||
make -C ../../../library/util_tdd_sync clean
|
||||
make -C ../../../library/util_upack clean
|
||||
make -C ../../../library/util_wfifo clean
|
||||
|
||||
|
||||
fmcomms2_zc706pr.sdk/system_top.hdf: $(M_DEPS)
|
||||
rm -rf $(M_FLIST)
|
||||
$(M_VIVADO) system_project.tcl >> fmcomms2_zc706pr_vivado.log 2>&1
|
||||
fmcomms2_zc706.sdk/system_top.hdf: $(M_DEPS)
|
||||
-rm -rf $(M_FLIST)
|
||||
$(M_VIVADO) system_project.tcl >> fmcomms2_zc706_vivado.log 2>&1
|
||||
|
||||
|
||||
lib:
|
||||
|
|
@ -68,6 +80,7 @@ lib:
|
|||
make -C ../../../library/axi_hdmi_tx
|
||||
make -C ../../../library/axi_spdif_tx
|
||||
make -C ../../../library/util_cpack
|
||||
make -C ../../../library/util_tdd_sync
|
||||
make -C ../../../library/util_upack
|
||||
make -C ../../../library/util_wfifo
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,32 @@
|
|||
|
||||
|
||||
## requires partial reconfiguration license
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
set mode 0
|
||||
if {$::argc > 0} {
|
||||
set mode [lindex $argv 0]
|
||||
}
|
||||
|
||||
if {$mode == 0} {
|
||||
|
||||
adi_project_create fmcomms2_zc706
|
||||
adi_project_files fmcomms2_zc706 [list \
|
||||
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
|
||||
"$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \
|
||||
"$ad_hdl_dir/library/prcfg/default/prcfg_dac.v" \
|
||||
"$ad_hdl_dir/library/prcfg/default/prcfg_adc.v" \
|
||||
"../common/prcfg.v" \
|
||||
"../zc706/system_constr.xdc" \
|
||||
"system_top.v" ]
|
||||
|
||||
adi_project_run fmcomms2_zc706
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
adi_project_create fmcomms2_zc706 1
|
||||
adi_project_synth fmcomms2_zc706 "" \
|
||||
[list "system_top.v" \
|
||||
|
|
|
|||
|
|
@ -88,8 +88,13 @@ module system_top (
|
|||
tx_data_out_p,
|
||||
tx_data_out_n,
|
||||
|
||||
gpio_txnrx,
|
||||
gpio_enable,
|
||||
enable,
|
||||
txnrx,
|
||||
|
||||
tdd_sync,
|
||||
|
||||
gpio_muxout_tx,
|
||||
gpio_muxout_rx,
|
||||
gpio_resetb,
|
||||
gpio_sync,
|
||||
gpio_en_agc,
|
||||
|
|
@ -99,7 +104,12 @@ module system_top (
|
|||
spi_csn,
|
||||
spi_clk,
|
||||
spi_mosi,
|
||||
spi_miso);
|
||||
spi_miso,
|
||||
|
||||
spi_udc_csn_tx,
|
||||
spi_udc_csn_rx,
|
||||
spi_udc_sclk,
|
||||
spi_udc_data);
|
||||
|
||||
inout [14:0] ddr_addr;
|
||||
inout [ 2:0] ddr_ba;
|
||||
|
|
@ -150,8 +160,13 @@ module system_top (
|
|||
output [ 5:0] tx_data_out_p;
|
||||
output [ 5:0] tx_data_out_n;
|
||||
|
||||
inout gpio_txnrx;
|
||||
inout gpio_enable;
|
||||
output enable;
|
||||
output txnrx;
|
||||
|
||||
inout tdd_sync;
|
||||
|
||||
inout gpio_muxout_tx;
|
||||
inout gpio_muxout_rx;
|
||||
inout gpio_resetb;
|
||||
inout gpio_sync;
|
||||
inout gpio_en_agc;
|
||||
|
|
@ -163,12 +178,16 @@ module system_top (
|
|||
output spi_mosi;
|
||||
input spi_miso;
|
||||
|
||||
output spi_udc_csn_tx;
|
||||
output spi_udc_csn_rx;
|
||||
output spi_udc_sclk;
|
||||
output spi_udc_data;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
|
||||
wire clk;
|
||||
wire dma_dac_i0_enable;
|
||||
wire [15:0] dma_dac_i0_data;
|
||||
|
|
@ -218,7 +237,6 @@ module system_top (
|
|||
wire core_adc_q1_enable;
|
||||
wire [15:0] core_adc_q1_data;
|
||||
wire core_adc_q1_valid;
|
||||
|
||||
wire [31:0] adc_gpio_input;
|
||||
wire [31:0] adc_gpio_output;
|
||||
wire [31:0] dac_gpio_input;
|
||||
|
|
@ -254,6 +272,7 @@ module system_top (
|
|||
.dio_p (tdd_sync));
|
||||
|
||||
// prcfg instance
|
||||
|
||||
prcfg i_prcfg (
|
||||
.clk (clk),
|
||||
.adc_gpio_input (adc_gpio_input),
|
||||
|
|
@ -307,8 +326,7 @@ module system_top (
|
|||
.core_adc_i1_valid (core_adc_i1_valid),
|
||||
.core_adc_q1_enable (core_adc_q1_enable),
|
||||
.core_adc_q1_data (core_adc_q1_data),
|
||||
.core_adc_q1_valid (core_adc_q1_valid)
|
||||
);
|
||||
.core_adc_q1_valid (core_adc_q1_valid));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
|
|
@ -371,13 +389,27 @@ module system_top (
|
|||
.spi0_sdi_i (spi_miso),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (spi_mosi),
|
||||
.spi1_clk_i (1'b0),
|
||||
.spi1_clk_o (spi_udc_sclk),
|
||||
.spi1_csn_0_o (spi_udc_csn_tx),
|
||||
.spi1_csn_1_o (spi_udc_csn_rx),
|
||||
.spi1_csn_2_o (),
|
||||
.spi1_csn_i (1'b1),
|
||||
.spi1_sdi_i (1'b0),
|
||||
.spi1_sdo_i (spi_udc_data),
|
||||
.spi1_sdo_o (spi_udc_data),
|
||||
.tdd_sync_i (tdd_sync_i),
|
||||
.tdd_sync_o (tdd_sync_o),
|
||||
.tdd_sync_t (tdd_sync_t),
|
||||
.tx_clk_out_n (tx_clk_out_n),
|
||||
.tx_clk_out_p (tx_clk_out_p),
|
||||
.tx_data_out_n (tx_data_out_n),
|
||||
.tx_data_out_p (tx_data_out_p),
|
||||
.tx_frame_out_n (tx_frame_out_n),
|
||||
.tx_frame_out_p (tx_frame_out_p),
|
||||
// pr related ports
|
||||
.txnrx (txnrx),
|
||||
.up_enable (gpio_o[47]),
|
||||
.up_txnrx (gpio_o[48]),
|
||||
.clk (clk),
|
||||
.up_adc_gpio_in (adc_gpio_input),
|
||||
.up_adc_gpio_out (adc_gpio_output),
|
||||
|
|
@ -430,8 +462,7 @@ module system_top (
|
|||
.core_adc_i1_valid (core_adc_i1_valid),
|
||||
.core_adc_q1_enable (core_adc_q1_enable),
|
||||
.core_adc_q1_data (core_adc_q1_data),
|
||||
.core_adc_q1_valid (core_adc_q1_valid)
|
||||
);
|
||||
.core_adc_q1_valid (core_adc_q1_valid));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue