common: Add xilinx ila utils
Signed-off-by: David Winter <david.winter@analog.com>main
David Winter
Laszlo Nagy
parent
638491d502
commit
69f1d05e7c
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## Instantiate Xilinx Virtual Cable debug bridge
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# This procedure will instantiate the two debug bridges that make
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# up the XVC logic, and hook them up to the main CPU interconnect
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#
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# \param[clk] - Clock input
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#
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proc ad_ila_setup_xvc {cpu_addr} {
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# AXI to DBSCAN
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ad_ip_instance debug_bridge debug_bridge_0 [list \
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C_DEBUG_MODE {2} \
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C_NUM_BS_MASTER {1} \
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C_BSCAN_MUX {2} \
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C_XVC_HW_ID {0x0002} \
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]
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# DBSCAN to Debug Hub
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ad_ip_instance debug_bridge debug_bridge_1 [list \
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C_DEBUG_MODE {1} \
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]
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ad_connect sys_cpu_clk debug_bridge_0/s_axi_aclk
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ad_connect sys_cpu_clk debug_bridge_1/clk
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ad_connect sys_cpu_resetn debug_bridge_0/s_axi_aresetn
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ad_connect debug_bridge_0/m0_bscan debug_bridge_1/S_BSCAN
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ad_cpu_interconnect $cpu_addr debug_bridge_0
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}
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global _ad_ila_cnt
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## Instantiate an ILA core that can be used to monitor interfaces
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#
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# \param[clk] - The clock domain to which the interfaces are aligned
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# \param[resetn] - The clock domains inverted reset signal
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# \param[depth] - The ILA depth in samples, must be in 2**k, for k in [10, 17]
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# \param[input_pipe_stages] - Input pipeline stages of the ILA core
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# \param[advanced_trigger] - Enable advanced trigger options in the ILA
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# \param[capture_control] - Enable capture control logic in the ILA
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# \param[comparator_count] - Comparator count
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#
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proc ad_ila_setup_intf {clk \
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resetn \
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{depth 1024} \
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{input_pipe_stages 1} \
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{advanced_trigger {TRUE}} \
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{capture_control {TRUE}} \
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{comparator_count {0}} \
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} {
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set name "ila_intf_$clk"
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_ad_ila_setup $name $clk INTERFACE $depth $input_pipe_stages $advanced_trigger $capture_control $comparator_count
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ad_connect $resetn $name/resetn
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}
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## Instantiate an ILA core that can be used to monitor non-interface signals
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#
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# \param[clk] - The clock domain to which the interfaces are aligned
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# \param[depth] - The ILA depth in samples, must be in 2**k, for k in [10, 17]
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# \param[input_pipe_stages] - Input pipeline stages of the ILA core
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# \param[advanced_trigger] - Enable advanced trigger options in the ILA
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# \param[capture_control] - Enable capture control logic in the ILA
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# \param[comparator_count] - Comparator count
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#
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proc ad_ila_setup {clk \
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{depth 1024} \
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{input_pipe_stages 1} \
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{advanced_trigger {TRUE}} \
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{capture_control {TRUE}} \
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{comparator_count {0}} \
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} {
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_ad_ila_setup "ila_$clk" $clk NATIVE $depth $input_pipe_stages $advanced_trigger $capture_control $comparator_count
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}
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## Internal use only, backend for ad_ila_setup{,_intf}
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proc _ad_ila_setup {name \
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clk \
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ila_type \
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{depth 1024} \
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{input_pipe_stages 1} \
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{advanced_trigger {TRUE}} \
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{capture_control {TRUE}} \
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{comparator_count {0}} \
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} {
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global _ad_ila_cnt
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if {$comparator_count == 0} {
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set comparator_count [expr {1 + !!$capture_control}]
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}
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ad_ip_instance system_ila $name [ list \
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ALL_PROBE_SAME_MU {TRUE} \
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ALL_PROBE_SAME_MU_CNT $comparator_count \
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C_MON_TYPE $ila_type \
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C_ADV_TRIGGER $advanced_trigger \
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C_EN_STRG_QUAL $capture_control \
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C_INPUT_PIPE_STAGES $input_pipe_stages \
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C_DATA_DEPTH $depth ]
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ad_connect $clk $name/clk
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set _ad_ila_cnt($name) 0
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}
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## Connect signal to signal ILA core
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#
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# \param[clk] - The clock domain to which the interfaces are aligned
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# \param[target] - The target pin/port
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#
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proc ad_ila_connect {clk target} {
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global _ad_ila_cnt
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set name "ila_$clk"
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set id $_ad_ila_cnt($name)
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set new_id [expr {$id + 1}]
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set _ad_ila_cnt($name) $new_id
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puts "Connecting ila probe ${id}, new_id: ${new_id}"
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ad_ip_parameter $name CONFIG.C_NUM_OF_PROBES $new_id
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ad_connect $target [get_bd_pins "$name/probe${id}"]
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}
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## Connect *any* interface to previously instantiated intf ILA core
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#
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# \param[clk] - The clock domain to which the interfaces are aligned
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# \param[target] - The target interface pin/port
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#
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proc ad_ila_connect_intf {clk target} {
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global _ad_ila_cnt
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set name "ila_intf_$clk"
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set id $_ad_ila_cnt($name)
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set new_id [expr {$id + 1}]
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set _ad_ila_cnt($name) $new_id
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puts "Connecting ila slot ${id}, new_id: ${new_id}"
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ad_ip_parameter $name CONFIG.C_NUM_MONITOR_SLOTS $new_id
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set intf_vlnv [get_property VLNV [get_bd_intf_pins $target]]
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ad_ip_parameter $name CONFIG.C_SLOT_${id}_INTF_TYPE $intf_vlnv
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ad_connect $target [get_bd_intf_pins $name/SLOT_${id}_*]
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}
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