axi_i2s/axi_spdif: Create clock and reset interface for DMA bus
This avoids some critical warnings from Vivado that the DMA bus does not has any associated clocks. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
parent
7682400a28
commit
6a08f26905
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@ -28,6 +28,8 @@ adi_add_bus "DMA_REQ_RX" "axis" "master" \
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{"DMA_REQ_RX_DRREADY" "TREADY"} \
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{"DMA_REQ_RX_DRREADY" "TREADY"} \
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{"DMA_REQ_RX_DRTYPE" "TUSER"} \
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{"DMA_REQ_RX_DRTYPE" "TUSER"} \
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{"DMA_REQ_RX_DRLAST" "TLAST"} ]
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{"DMA_REQ_RX_DRLAST" "TLAST"} ]
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# Clock and reset are for both DMA_REQ and DMA_ACK
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adi_add_bus_clock "DMA_REQ_RX_ACLK" "DMA_REQ_RX:DMA_ACK_RX" "DMA_REQ_RX_RSTN"
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adi_add_bus "DMA_ACK_TX" "axis" "slave" \
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adi_add_bus "DMA_ACK_TX" "axis" "slave" \
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[list {"DMA_REQ_TX_DAVALID" "TVALID"} \
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[list {"DMA_REQ_TX_DAVALID" "TVALID"} \
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@ -38,6 +40,8 @@ adi_add_bus "DMA_REQ_TX" "axis" "master" \
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{"DMA_REQ_TX_DRREADY" "TREADY"} \
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{"DMA_REQ_TX_DRREADY" "TREADY"} \
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{"DMA_REQ_TX_DRTYPE" "TUSER"} \
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{"DMA_REQ_TX_DRTYPE" "TUSER"} \
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{"DMA_REQ_TX_DRLAST" "TLAST"} ]
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{"DMA_REQ_TX_DRLAST" "TLAST"} ]
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# Clock and reset are for both DMA_REQ and DMA_ACK
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adi_add_bus_clock "DMA_REQ_TX_ACLK" "DMA_REQ_TX:DMA_ACK_TX" "DMA_REQ_TX_RSTN"
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adi_set_bus_dependency "S_AXIS" "S_AXIS" \
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adi_set_bus_dependency "S_AXIS" "S_AXIS" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
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@ -31,6 +31,9 @@ adi_add_bus "DMA_REQ" "axis" "master" \
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{"DMA_REQ_DRTYPE" "TUSER"} \
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{"DMA_REQ_DRTYPE" "TUSER"} \
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{"DMA_REQ_DRLAST" "TLAST"} ]
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{"DMA_REQ_DRLAST" "TLAST"} ]
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# Clock and reset are for both DMA_REQ and DMA_ACK
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adi_add_bus_clock "DMA_REQ_ACLK" "DMA_REQ:DMA_ACK" "DMA_REQ_RSTN"
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adi_set_bus_dependency "S_AXIS" "S_AXIS" \
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adi_set_bus_dependency "S_AXIS" "S_AXIS" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
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