zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ad9434: Fix the processor read interface 

Fix the processor read interface, preventing to have nets with multiple drivers. Made a few cosmetic changes in the code too.
main
Istvan Csomortani 2014-09-25 16:51:58 +03:00
parent ccb0b135ca
commit 6a09a1ed19
1 changed files with 25 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
library/axi_ad9434/axi_ad9434_core.v
View File

@ -65,7 +65,9 @@ module axi_ad9434_core (
drp_rdata, drp_rdata,
drp_ready, drp_ready,
drp_locked, drp_locked,
// delay interface // delay interface
delay_clk, delay_clk,
delay_rst, delay_rst,
delay_sel, delay_sel,
@ -75,7 +77,9 @@ module axi_ad9434_core (
delay_rdata, delay_rdata,
delay_ack_t, delay_ack_t,
delay_locked, delay_locked,
// processor interface // processor interface
up_rstn, up_rstn,
up_clk, up_clk,
up_sel, up_sel,
@ -86,6 +90,7 @@ module axi_ad9434_core (
up_ack, up_ack,
// status and control signals // status and control signals
mmcm_rst, mmcm_rst,
adc_rst, adc_rst,
adc_status); adc_status);
@ -139,6 +144,9 @@ module axi_ad9434_core (
output adc_rst; output adc_rst;
input adc_status; input adc_status;
reg [31:0] up_rdata;
reg up_ack;
// internal signals // internal signals
wire up_status_pn_err_s; wire up_status_pn_err_s;
wire up_status_pn_oos_s; wire up_status_pn_oos_s;
@ -180,6 +188,18 @@ module axi_ad9434_core (
end end
endgenerate endgenerate
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
up_ack <= up_ack_s[0] | up_ack_s[1];
end
end
up_adc_common #( up_adc_common #(
.PCORE_ID(PCORE_ID)) .PCORE_ID(PCORE_ID))
i_adc_common( i_adc_common(
@ -224,8 +244,8 @@ module axi_ad9434_core (
.up_wr(up_wr), .up_wr(up_wr),
.up_addr(up_addr), .up_addr(up_addr),
.up_wdata(up_wdata), .up_wdata(up_wdata),
.up_rdata(up_rdata), .up_rdata(up_rdata_s[0]),
.up_ack(up_ack)); .up_ack(up_ack_s[0]));
up_adc_channel #( up_adc_channel #(
.PCORE_ADC_CHID(0)) .PCORE_ADC_CHID(0))
@ -246,7 +266,7 @@ module axi_ad9434_core (
.adc_data_sel(), .adc_data_sel(),
.adc_pn_err(adc_pn_err_s), .adc_pn_err(adc_pn_err_s),
.adc_pn_oos(adc_pn_oos_s), .adc_pn_oos(adc_pn_oos_s),
.adc_or(adc_or_s), .adc_or(adc_or),
.up_adc_pn_err(up_status_pn_err_s), .up_adc_pn_err(up_status_pn_err_s),
.up_adc_pn_oos(up_status_pn_oos_s), .up_adc_pn_oos(up_status_pn_oos_s),
.up_adc_or(up_status_or_s), .up_adc_or(up_status_or_s),
@ -270,7 +290,7 @@ module axi_ad9434_core (
.up_wr(up_wr), .up_wr(up_wr),
.up_addr(up_addr), .up_addr(up_addr),
.up_wdata(up_wdata), .up_wdata(up_wdata),
.up_rdata(up_rdata), .up_rdata(up_rdata_s[1]),
.up_ack(up_ack)); .up_ack(up_ack_s[1]));
endmodule endmodule