projects/fmcomms8: Expose jesd params, add support for TX_JESD_L=4
Liviu.Iacob
LIacob106
parent
56691bd440
commit
6a583a8ace
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@ -7,40 +7,54 @@ create_bd_port -dir I core_clk_d
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create_bd_port -dir I dac_fifo_bypass
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#
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# Parameter description:
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# [TX/RX/RX_OS]_JESD_M : Number of converters per link
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# [TX/RX/RX_OS]_JESD_L : Number of lanes per link
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# [TX/RX/RX_OS]_JESD_S : Number of samples per frame
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# [TX/RX/RX_OS]_JESD_NP : Number of bits per sample
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#
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set MAX_TX_NUM_OF_LANES 8
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set MAX_RX_NUM_OF_LANES 4
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set MAX_RX_OS_NUM_OF_LANES 4
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# TX parameters
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set TX_NUM_OF_LANES 8 ; # L
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set TX_NUM_OF_CONVERTERS 8 ; # M
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set TX_SAMPLES_PER_FRAME 1 ; # S
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set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
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set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
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set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / \
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($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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# RX parameters
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set RX_NUM_OF_LANES 4 ; # L
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set RX_NUM_OF_CONVERTERS 8 ; # M
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set RX_SAMPLES_PER_FRAME 1 ; # S
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set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
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set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
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set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL 1 ; # L * 32 / (M * N)
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / \
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($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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# RX Observation parameters
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set OBS_NUM_OF_LANES 4 ; # L
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set OBS_NUM_OF_CONVERTERS 4 ; # M
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set OBS_SAMPLES_PER_FRAME 1 ; # S
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set OBS_SAMPLE_WIDTH 16 ; # N/NP
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set RX_OS_NUM_OF_LANES $ad_project_params(RX_OS_JESD_L) ; # L
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set RX_OS_NUM_OF_CONVERTERS $ad_project_params(RX_OS_JESD_M) ; # M
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set RX_OS_SAMPLES_PER_FRAME $ad_project_params(RX_OS_JESD_S) ; # S
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set RX_OS_SAMPLE_WIDTH 16 ; # N/NP
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set OBS_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 32 / \
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($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)] ; # L * 32 / (M * N)
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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set dac_fifo_name axi_adrv9009_fmc_tx_fifo
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set dac_data_width 256
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set dac_dma_data_width 256
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set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
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ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
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ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width
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ad_ip_instance axi_adxcvr axi_adrv9009_fmc_tx_xcvr
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ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.NUM_OF_LANES $MAX_TX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_adrv9009_fmc_tx_xcvr CONFIG.TX_OR_RX_N 1
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@ -65,13 +79,13 @@ ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 256
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.MAX_BYTES_PER_BURST 512
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ad_ip_instance axi_adxcvr axi_adrv9009_fmc_rx_xcvr
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ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.NUM_OF_LANES $MAX_RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.TX_OR_RX_N 0
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@ -96,26 +110,26 @@ ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES]
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ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance axi_adxcvr axi_adrv9009_fmc_obs_xcvr
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ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.NUM_OF_LANES $MAX_RX_OS_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.TX_OR_RX_N 0
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adi_axi_jesd204_rx_create axi_adrv9009_fmc_obs_jesd $OBS_NUM_OF_LANES
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adi_axi_jesd204_rx_create axi_adrv9009_fmc_obs_jesd $RX_OS_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_fmc_obs_cpack [list \
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NUM_OF_CHANNELS $OBS_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $OBS_SAMPLES_PER_CHANNEL\
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SAMPLE_DATA_WIDTH $OBS_SAMPLE_WIDTH \
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NUM_OF_CHANNELS $RX_OS_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_OS_SAMPLES_PER_CHANNEL\
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SAMPLE_DATA_WIDTH $RX_OS_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create obs_adrv9009_fmc_tpl_core $OBS_NUM_OF_LANES \
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$OBS_NUM_OF_CONVERTERS \
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$OBS_SAMPLES_PER_FRAME \
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$OBS_SAMPLE_WIDTH
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adi_tpl_jesd204_rx_create obs_adrv9009_fmc_tpl_core $RX_OS_NUM_OF_LANES \
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$RX_OS_NUM_OF_CONVERTERS \
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$RX_OS_SAMPLES_PER_FRAME \
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$RX_OS_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9009_fmc_obs_dma
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_TYPE_SRC 2
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@ -125,12 +139,12 @@ ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_OS_NUM_OF_LANES]
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ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance util_adxcvr util_adrv9009_fmc_xcvr
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.RX_NUM_OF_LANES [expr $RX_NUM_OF_LANES+$OBS_NUM_OF_LANES]
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES+$MAX_RX_OS_NUM_OF_LANES]
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.TX_OUT_DIV 2
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.CPLL_FBDIV 4
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ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.RX_CLK25_DIV 10
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@ -162,7 +176,12 @@ ad_xcvrpll axi_adrv9009_fmc_obs_xcvr/up_pll_rst util_adrv9009_fmc_xcvr/up_cpll_
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ad_connect sys_cpu_resetn util_adrv9009_fmc_xcvr/up_rstn
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ad_connect sys_cpu_clk util_adrv9009_fmc_xcvr/up_clk
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_tx_xcvr axi_adrv9009_fmc_tx_jesd {1 0 2 3 4 5 6 7} core_clk_c
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if {$TX_NUM_OF_LANES == 8} {
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_tx_xcvr axi_adrv9009_fmc_tx_jesd {1 0 2 3 4 5 6 7} core_clk_c
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} else {
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#TX_JESD_L=4, it is recommanded to use RX_OS_JESD_M=TX_JESD_M because they share the same device clock
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_tx_xcvr axi_adrv9009_fmc_tx_jesd {1 0 2 3 4 5 6 7} core_clk_c {} $MAX_TX_NUM_OF_LANES {1 0 4 5}
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}
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_rx_xcvr axi_adrv9009_fmc_rx_jesd {0 1 4 5} core_clk_d
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ad_xcvrcon util_adrv9009_fmc_xcvr axi_adrv9009_fmc_obs_xcvr axi_adrv9009_fmc_obs_jesd {2 3 6 7} core_clk_c
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@ -225,7 +244,7 @@ ad_connect core_clk_c_rstgen/peripheral_reset util_fmc_obs_cpack/reset
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ad_connect core_clk_c axi_adrv9009_fmc_obs_dma/fifo_wr_clk
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ad_connect obs_adrv9009_fmc_tpl_core/adc_valid_0 util_fmc_obs_cpack/fifo_wr_en
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for {set i 0} {$i < $OBS_NUM_OF_CONVERTERS} {incr i} {
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for {set i 0} {$i < $RX_OS_NUM_OF_CONVERTERS} {incr i} {
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ad_connect obs_adrv9009_fmc_tpl_core/adc_enable_$i util_fmc_obs_cpack/enable_$i
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ad_connect obs_adrv9009_fmc_tpl_core/adc_data_$i util_fmc_obs_cpack/fifo_wr_data_$i
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}
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@ -3,7 +3,17 @@ source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project fmcomms8_zcu102
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adi_project fmcomms8_zcu102 0 [list \
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RX_JESD_M [get_env_param RX_JESD_M 8 ] \
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RX_JESD_L [get_env_param RX_JESD_L 4 ] \
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RX_JESD_S [get_env_param RX_JESD_S 1 ] \
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TX_JESD_M [get_env_param TX_JESD_M 8 ] \
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TX_JESD_L [get_env_param TX_JESD_L 8 ] \
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TX_JESD_S [get_env_param TX_JESD_S 1 ] \
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RX_OS_JESD_M [get_env_param RX_OS_JESD_M 4 ] \
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RX_OS_JESD_L [get_env_param RX_OS_JESD_L 4 ] \
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RX_OS_JESD_S [get_env_param RX_OS_JESD_S 1 ] \
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]
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adi_project_files fmcomms8_zcu102 [list \
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"system_top.v" \
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"system_constr.xdc"\
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