From 6a681b9e8d2a4f0ebd94f0ec18598b4b68382544 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Wed, 29 Sep 2021 16:06:08 +0100 Subject: [PATCH] common/vmk180_es1: Initial version --- .../vmk180_es1/vmk180_es1_system_bd.tcl | 2 ++ .../vmk180_es1/vmk180_es1_system_constr.xdc | 24 +++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 projects/common/vmk180_es1/vmk180_es1_system_bd.tcl create mode 100644 projects/common/vmk180_es1/vmk180_es1_system_constr.xdc diff --git a/projects/common/vmk180_es1/vmk180_es1_system_bd.tcl b/projects/common/vmk180_es1/vmk180_es1_system_bd.tcl new file mode 100644 index 000000000..0461e6e3f --- /dev/null +++ b/projects/common/vmk180_es1/vmk180_es1_system_bd.tcl @@ -0,0 +1,2 @@ +source $ad_hdl_dir/projects/common/vmk180/vmk180_system_bd.tcl + diff --git a/projects/common/vmk180_es1/vmk180_es1_system_constr.xdc b/projects/common/vmk180_es1/vmk180_es1_system_constr.xdc new file mode 100644 index 000000000..871065301 --- /dev/null +++ b/projects/common/vmk180_es1/vmk180_es1_system_constr.xdc @@ -0,0 +1,24 @@ + +create_clock -period 5.000 -name sys_clk_p [get_ports sys_clk_p] + +set_property PACKAGE_PIN AF43 [get_ports sys_clk_n] +set_property PACKAGE_PIN AE42 [get_ports sys_clk_p] + +# Define SPI clock +create_clock -name spi0_clk -period 40 [get_pins -hier */EMIOSPI0SCLKO] +create_clock -name spi1_clk -period 40 [get_pins -hier */EMIOSPI1SCLKO] + +# GPIOs +# (switches, leds and such) +set_property -dict {PACKAGE_PIN H34 IOSTANDARD LVCMOS18} [get_ports gpio_led[0]] ; # DS6 +set_property -dict {PACKAGE_PIN J33 IOSTANDARD LVCMOS18} [get_ports gpio_led[1]] ; # DS5 +set_property -dict {PACKAGE_PIN K36 IOSTANDARD LVCMOS18} [get_ports gpio_led[2]] ; # DS4 +set_property -dict {PACKAGE_PIN L35 IOSTANDARD LVCMOS18} [get_ports gpio_led[3]] ; # DS3 + +set_property -dict {PACKAGE_PIN J35 IOSTANDARD LVCMOS18} [get_ports gpio_dip_sw[0]] ; # SW6.1 +set_property -dict {PACKAGE_PIN J34 IOSTANDARD LVCMOS18} [get_ports gpio_dip_sw[1]] ; # SW6.2 +set_property -dict {PACKAGE_PIN H37 IOSTANDARD LVCMOS18} [get_ports gpio_dip_sw[2]] ; # SW6.3 +set_property -dict {PACKAGE_PIN H36 IOSTANDARD LVCMOS18} [get_ports gpio_dip_sw[3]] ; # SW6.4 + +set_property -dict {PACKAGE_PIN G37 IOSTANDARD LVCMOS18} [get_ports gpio_pb[0]] ; # SW4 +set_property -dict {PACKAGE_PIN G36 IOSTANDARD LVCMOS18} [get_ports gpio_pb[1]] ; # SW5