axi_ad9625: Port redeclaration as a wire is not allowed

2017-04-20 10:49:24 +03:00 · 2017-04-20 10:49:24 +03:00 · 6ab8624a06
parent 0ffbe50163
commit 6ab8624a06
1 changed files with 6 additions and 7 deletions
--- a/library/axi_ad9625/axi_ad9625.v
+++ b/library/axi_ad9625/axi_ad9625.v
@ -98,7 +98,6 @@ module axi_ad9625 #(

  // internal clocks & resets

-  wire            adc_rst;
  wire            up_rstn;
  wire            up_clk;