up_axi: Prevent read and write requests from racing against each other

Make sure that if a read and a write request arrive on the very same clock
cycle to only accept one of them. The simple solution chosen here is to only
accept the write request when this happens and delay the acceptance of the
read request until the write request is finished.

This solution is not fair since a write request will always take precedence,
which in theory allows the write bus to starve the read bus. But in practice
we should never see that many write requests that we are unable to answer
the read request.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

library/common/up_axi.v

@@ -151,7 +151,7 @@ module up_axi (
     (up_axi_awvalid & up_axi_wvalid & ~up_axi_access) : 1'b0;
 
   assign up_axi_rd_s = ((up_axi_araddr >= PCORE_BASEADDR) && (up_axi_araddr <= PCORE_HIGHADDR)) ?
-    (up_axi_arvalid & ~up_axi_access) : 1'b0;
+    (up_axi_arvalid & ~up_axi_access & ~up_axi_wr_s) : 1'b0;
 
   assign up_axi_ack_s = ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) ||
     ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1));