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library: Fixed changes related to parameters

main
Adrian Costina 2015-08-20 18:13:54 +03:00
parent 9e5e7d6805
commit 6ae0c8f85e
4 changed files with 20 additions and 20 deletions
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4
library/common/ad_csc_1_mul.v
View File

@ -103,8 +103,8 @@ module ad_csc_1_mul (
MULT_MACRO #(
.LATENCY (3),
.A_DATA_WIDTH (17),
.B_DATA_WIDTH (9))
.WIDTH_A (17),
.WIDTH_B (9))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),

4
library/common/ad_mul.v
View File

@ -85,8 +85,8 @@ module ad_mul (
MULT_MACRO #(
.LATENCY (3),
.A_DATA_WIDTH (17),
.B_DATA_WIDTH (17))
.WIDTH_A (17),
.WIDTH_B (17))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),

20
library/common/ad_serdes_in.v
View File

@ -176,7 +176,7 @@ module ad_serdes_in (
// Note: The first sample in time will be data_s7, the last data_s0!
if(DDR_OR_SDR_N == SDR) begin
ISERDES_OR_DDR_NE2 #(
ISERDESE2 #(
.DATA_RATE("SDR"),
.DATA_WIDTH(DATA_WIDTH),
.DYN_CLKDIV_INV_EN("FALSE"),
@ -189,12 +189,12 @@ module ad_serdes_in (
.IOBDELAY("IFD"),
.NUM_CE(2),
.OFB_USED("FALSE"),
.SERDES_OR_DDR_N_MODE("MASTER"),
.SERDES_MODE("MASTER"),
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
.SRVAL_Q4(1'b0))
ISERDES_OR_DDR_NE2_inst (
ISERDESE2_inst (
.O(),
.Q1(data_s0),
.Q2(data_s1),
@ -226,7 +226,7 @@ module ad_serdes_in (
);
end else begin
ISERDES_OR_DDR_NE2 #(
ISERDESE2 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(DATA_WIDTH),
.DYN_CLKDIV_INV_EN("FALSE"),
@ -239,12 +239,12 @@ module ad_serdes_in (
.IOBDELAY("IFD"),
.NUM_CE(2),
.OFB_USED("FALSE"),
.SERDES_OR_DDR_N_MODE("MASTER"),
.SERDES_MODE("MASTER"),
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
.SRVAL_Q4(1'b0))
ISERDES_OR_DDR_NE2_inst (
ISERDESE2_inst (
.O(),
.Q1(data_s0),
.Q2(data_s1),
@ -304,7 +304,7 @@ module ad_serdes_in (
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
ISERDES_OR_DDR_NE1 #(
ISERDESE1 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(DATA_WIDTH),
.DYN_CLKDIV_INV_EN("FALSE"),
@ -317,7 +317,7 @@ module ad_serdes_in (
.IOBDELAY("NONE"),
.NUM_CE(1),
.OFB_USED("FALSE"),
.SERDES_OR_DDR_N_MODE("MASTER"),
.SERDES_MODE("MASTER"),
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
@ -349,7 +349,7 @@ module ad_serdes_in (
.SHIFTIN2(1'b0)
);
ISERDES_OR_DDR_NE1 #(
ISERDESE1 #(
.DATA_RATE("DDR"),
.DATA_WIDTH(DATA_WIDTH),
.DYN_CLKDIV_INV_EN("FALSE"),
@ -362,7 +362,7 @@ module ad_serdes_in (
.IOBDELAY("NONE"),
.NUM_CE(1),
.OFB_USED("FALSE"),
.SERDES_OR_DDR_N_MODE("SLAVE"),
.SERDES_MODE("SLAVE"),
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),

12
library/common/ad_serdes_out.v
View File

@ -119,12 +119,12 @@ module ad_serdes_out (
end
if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_7SERIES)) begin
OSERDES_OR_DDR_NE2 #(
OSERDESE2 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (8),
.TRISTATE_WIDTH (1),
.SERDES_OR_DDR_N_MODE ("MASTER"))
.SERDES_MODE ("MASTER"))
i_serdes (
.D1 (data_s0[l_inst]),
.D2 (data_s1[l_inst]),
@ -156,13 +156,13 @@ module ad_serdes_out (
end
if ((SERDES_OR_DDR_N == 1) && (DEVICE_TYPE == DEVICE_6SERIES)) begin
OSERDES_OR_DDR_NE1 #(
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (8),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_OR_DDR_N_MODE ("MASTER"))
.SERDES_MODE ("MASTER"))
i_serdes_m (
.D1 (data_s0[l_inst]),
.D2 (data_s1[l_inst]),
@ -193,13 +193,13 @@ module ad_serdes_out (
.TCE (1'b0),
.RST (rst));
OSERDES_OR_DDR_NE1 #(
OSERDESE1 #(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (8),
.INTERFACE_TYPE ("DEFAULT"),
.TRISTATE_WIDTH (1),
.SERDES_OR_DDR_N_MODE ("SLAVE"))
.SERDES_MODE ("SLAVE"))
i_serdes_s (
.D1 (1'b0),
.D2 (1'b0),