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axi_hdmi_tx: Add control to bypass chroma sub-sampler 

Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2015-06-30 21:11:58 +02:00
parent 68cb6df366
commit 6aee17da83
3 changed files with 37 additions and 12 deletions
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3
library/axi_hdmi_tx/axi_hdmi_tx.v
View File

@ -190,6 +190,7 @@ module axi_hdmi_tx (
wire up_rack_s; wire up_rack_s;
wire hdmi_full_range_s; wire hdmi_full_range_s;
wire hdmi_csc_bypass_s; wire hdmi_csc_bypass_s;
wire hdmi_ss_bypass_s;
wire [ 1:0] hdmi_srcsel_s; wire [ 1:0] hdmi_srcsel_s;
wire [23:0] hdmi_const_rgb_s; wire [23:0] hdmi_const_rgb_s;
wire [15:0] hdmi_hl_active_s; wire [15:0] hdmi_hl_active_s;
@ -269,6 +270,7 @@ module axi_hdmi_tx (
.hdmi_rst (hdmi_rst), .hdmi_rst (hdmi_rst),
.hdmi_full_range (hdmi_full_range_s), .hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s), .hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s), .hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s), .hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s), .hdmi_hl_active (hdmi_hl_active_s),
@ -354,6 +356,7 @@ module axi_hdmi_tx (
.vdma_fs_waddr (vdma_fs_waddr_s), .vdma_fs_waddr (vdma_fs_waddr_s),
.hdmi_full_range (hdmi_full_range_s), .hdmi_full_range (hdmi_full_range_s),
.hdmi_csc_bypass (hdmi_csc_bypass_s), .hdmi_csc_bypass (hdmi_csc_bypass_s),
.hdmi_ss_bypass (hdmi_ss_bypass_s),
.hdmi_srcsel (hdmi_srcsel_s), .hdmi_srcsel (hdmi_srcsel_s),
.hdmi_const_rgb (hdmi_const_rgb_s), .hdmi_const_rgb (hdmi_const_rgb_s),
.hdmi_hl_active (hdmi_hl_active_s), .hdmi_hl_active (hdmi_hl_active_s),

31
library/axi_hdmi_tx/axi_hdmi_tx_core.v
View File

@ -87,6 +87,7 @@ module axi_hdmi_tx_core (
hdmi_full_range, hdmi_full_range,
hdmi_csc_bypass, hdmi_csc_bypass,
hdmi_ss_bypass,
hdmi_srcsel, hdmi_srcsel,
hdmi_const_rgb, hdmi_const_rgb,
hdmi_hl_active, hdmi_hl_active,
@ -152,6 +153,7 @@ module axi_hdmi_tx_core (
input hdmi_full_range; input hdmi_full_range;
input hdmi_csc_bypass; input hdmi_csc_bypass;
input hdmi_ss_bypass;
input [ 1:0] hdmi_srcsel; input [ 1:0] hdmi_srcsel;
input [23:0] hdmi_const_rgb; input [23:0] hdmi_const_rgb;
input [15:0] hdmi_hl_active; input [15:0] hdmi_hl_active;
@ -213,6 +215,8 @@ module axi_hdmi_tx_core (
reg [23:0] hdmi_24_data = 'd0; reg [23:0] hdmi_24_data = 'd0;
reg hdmi_16_hsync = 'd0; reg hdmi_16_hsync = 'd0;
reg hdmi_16_vsync = 'd0; reg hdmi_16_vsync = 'd0;
reg hdmi_16_hsync_data_e = 'd0;
reg hdmi_16_vsync_data_e = 'd0;
reg hdmi_16_data_e = 'd0; reg hdmi_16_data_e = 'd0;
reg [15:0] hdmi_16_data = 'd0; reg [15:0] hdmi_16_data = 'd0;
reg hdmi_es_hs_de = 'd0; reg hdmi_es_hs_de = 'd0;
@ -473,18 +477,29 @@ module axi_hdmi_tx_core (
hdmi_24_data_e <= hdmi_csc_data_e_s; hdmi_24_data_e <= hdmi_csc_data_e_s;
hdmi_24_data <= hdmi_csc_data_s; hdmi_24_data <= hdmi_csc_data_s;
end end
hdmi_16_hsync <= hdmi_ss_hsync_s; if (hdmi_ss_bypass == 1'b1) begin
hdmi_16_vsync <= hdmi_ss_vsync_s; hdmi_16_hsync <= hdmi_24_hsync;
hdmi_16_data_e <= hdmi_ss_data_e_s; hdmi_16_vsync <= hdmi_24_vsync;
hdmi_16_data <= hdmi_ss_data_s; hdmi_16_hsync_data_e <= hdmi_24_hsync_data_e;
hdmi_16_vsync_data_e <= hdmi_24_vsync_data_e;
hdmi_16_data_e <= hdmi_24_data_e;
hdmi_16_data <= hdmi_24_data[15:0]; // Ignore the upper 8 bit
end else begin
hdmi_16_hsync <= hdmi_ss_hsync_s;
hdmi_16_vsync <= hdmi_ss_vsync_s;
hdmi_16_hsync_data_e <= hdmi_ss_hsync_data_e_s;
hdmi_16_vsync_data_e <= hdmi_ss_vsync_data_e_s;
hdmi_16_data_e <= hdmi_ss_data_e_s;
hdmi_16_data <= hdmi_ss_data_s;
end
end end
// hdmi embedded sync clipping // hdmi embedded sync clipping
assign hdmi_es_hs_de_s = hdmi_ss_hsync_data_e_s; assign hdmi_es_hs_de_s = hdmi_16_hsync_data_e;
assign hdmi_es_vs_de_s = hdmi_ss_vsync_data_e_s; assign hdmi_es_vs_de_s = hdmi_16_vsync_data_e;
assign hdmi_es_de_s = hdmi_ss_data_e_s; assign hdmi_es_de_s = hdmi_16_data_e;
assign hdmi_es_data_s = hdmi_ss_data_s; assign hdmi_es_data_s = hdmi_16_data;
always @(posedge hdmi_clk) begin always @(posedge hdmi_clk) begin
hdmi_es_hs_de <= hdmi_es_hs_de_s; hdmi_es_hs_de <= hdmi_es_hs_de_s;

15
library/common/up_hdmi_tx.v
View File

@ -47,6 +47,7 @@ module up_hdmi_tx (
hdmi_rst, hdmi_rst,
hdmi_full_range, hdmi_full_range,
hdmi_csc_bypass, hdmi_csc_bypass,
hdmi_ss_bypass,
hdmi_srcsel, hdmi_srcsel,
hdmi_const_rgb, hdmi_const_rgb,
hdmi_hl_active, hdmi_hl_active,
@ -95,6 +96,7 @@ module up_hdmi_tx (
output hdmi_rst; output hdmi_rst;
output hdmi_full_range; output hdmi_full_range;
output hdmi_csc_bypass; output hdmi_csc_bypass;
output hdmi_ss_bypass;
output [ 1:0] hdmi_srcsel; output [ 1:0] hdmi_srcsel;
output [23:0] hdmi_const_rgb; output [23:0] hdmi_const_rgb;
output [15:0] hdmi_hl_active; output [15:0] hdmi_hl_active;
@ -139,6 +141,7 @@ module up_hdmi_tx (
reg up_resetn = 'd0; reg up_resetn = 'd0;
reg up_full_range = 'd0; reg up_full_range = 'd0;
reg up_csc_bypass = 'd0; reg up_csc_bypass = 'd0;
reg up_ss_bypass = 'd0;
reg [ 1:0] up_srcsel = 'd1; reg [ 1:0] up_srcsel = 'd1;
reg [23:0] up_const_rgb = 'd0; reg [23:0] up_const_rgb = 'd0;
reg up_vdma_ovf = 'd0; reg up_vdma_ovf = 'd0;
@ -185,6 +188,7 @@ module up_hdmi_tx (
up_resetn <= 'd0; up_resetn <= 'd0;
up_full_range <= 'd0; up_full_range <= 'd0;
up_csc_bypass <= 'd0; up_csc_bypass <= 'd0;
up_ss_bypass <= 'd0;
up_srcsel <= 'd1; up_srcsel <= 'd1;
up_const_rgb <= 'd0; up_const_rgb <= 'd0;
up_vdma_ovf <= 'd0; up_vdma_ovf <= 'd0;
@ -210,6 +214,7 @@ module up_hdmi_tx (
up_resetn <= up_wdata[0]; up_resetn <= up_wdata[0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
up_ss_bypass <= up_wdata[2];
up_full_range <= up_wdata[1]; up_full_range <= up_wdata[1];
up_csc_bypass <= up_wdata[0]; up_csc_bypass <= up_wdata[0];
end end
@ -278,7 +283,7 @@ module up_hdmi_tx (
12'h001: up_rdata <= PCORE_ID; 12'h001: up_rdata <= PCORE_ID;
12'h002: up_rdata <= up_scratch; 12'h002: up_rdata <= up_scratch;
12'h010: up_rdata <= {31'd0, up_resetn}; 12'h010: up_rdata <= {31'd0, up_resetn};
12'h011: up_rdata <= {30'd0, up_full_range, up_csc_bypass}; 12'h011: up_rdata <= {29'd0, up_ss_bypass, up_full_range, up_csc_bypass};
12'h012: up_rdata <= {30'd0, up_srcsel}; 12'h012: up_rdata <= {30'd0, up_srcsel};
12'h013: up_rdata <= {8'd0, up_const_rgb}; 12'h013: up_rdata <= {8'd0, up_const_rgb};
12'h015: up_rdata <= up_hdmi_clk_count_s; 12'h015: up_rdata <= up_hdmi_clk_count_s;
@ -307,10 +312,11 @@ module up_hdmi_tx (
// hdmi control & status // hdmi control & status
up_xfer_cntrl #(.DATA_WIDTH(188)) i_hdmi_xfer_cntrl ( up_xfer_cntrl #(.DATA_WIDTH(189)) i_hdmi_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_full_range, .up_data_cntrl ({ up_ss_bypass,
up_full_range,
up_csc_bypass, up_csc_bypass,
up_srcsel, up_srcsel,
up_const_rgb, up_const_rgb,
@ -327,7 +333,8 @@ module up_hdmi_tx (
.up_xfer_done (), .up_xfer_done (),
.d_rst (hdmi_rst), .d_rst (hdmi_rst),
.d_clk (hdmi_clk), .d_clk (hdmi_clk),
.d_data_cntrl ({ hdmi_full_range, .d_data_cntrl ({ hdmi_ss_bypass,
hdmi_full_range,
hdmi_csc_bypass, hdmi_csc_bypass,
hdmi_srcsel, hdmi_srcsel,
hdmi_const_rgb, hdmi_const_rgb,