From 6b15704b7008cef6316e4f2e18f6e0a91c8a221f Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 1 Jul 2015 13:54:01 +0300 Subject: [PATCH] fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins. --- projects/fmcomms2/ac701/system_constr.xdc | 79 +-- projects/fmcomms2/ac701/system_top.v | 24 +- projects/fmcomms2/common/fmcomms2_bd.tcl | 354 +++++----- projects/fmcomms2/kc705/system_constr.xdc | 79 +-- projects/fmcomms2/kc705/system_top.v | 30 +- projects/fmcomms2/mitx045/system_constr.xdc | 129 ++-- projects/fmcomms2/mitx045/system_top.v | 594 +++++++++-------- projects/fmcomms2/rfsom/system_top.v | 699 ++++++++++---------- projects/fmcomms2/vc707/system_constr.xdc | 78 +-- projects/fmcomms2/vc707/system_top.v | 23 +- projects/fmcomms2/zc702/system_constr.xdc | 78 +-- projects/fmcomms2/zc702/system_top.v | 25 +- projects/fmcomms2/zc706/system_top.v | 622 ++++++++--------- projects/fmcomms2/zed/system_constr.xdc | 4 +- projects/fmcomms2/zed/system_top.v | 26 +- 15 files changed, 1479 insertions(+), 1365 deletions(-) diff --git a/projects/fmcomms2/ac701/system_constr.xdc b/projects/fmcomms2/ac701/system_constr.xdc index da1c8e1c6..d09a91497 100644 --- a/projects/fmcomms2/ac701/system_constr.xdc +++ b/projects/fmcomms2/ac701/system_constr.xdc @@ -1,39 +1,39 @@ # constraints -# ad9361 +# ad9361 -set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N @@ -50,13 +50,14 @@ set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[ set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N -set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N + +set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N # clocks diff --git a/projects/fmcomms2/ac701/system_top.v b/projects/fmcomms2/ac701/system_top.v index a01296477..ddcabbe7c 100644 --- a/projects/fmcomms2/ac701/system_top.v +++ b/projects/fmcomms2/ac701/system_top.v @@ -97,8 +97,9 @@ module system_top ( tx_data_out_p, tx_data_out_n, - gpio_txnrx, - gpio_enable, + txnrx, + enable, + gpio_resetb, gpio_sync, gpio_en_agc, @@ -167,8 +168,9 @@ module system_top ( output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_n; - inout gpio_txnrx; - inout gpio_enable; + output txnrx; + output enable; + inout gpio_resetb; inout gpio_sync; inout gpio_en_agc; @@ -190,12 +192,21 @@ module system_top ( wire spi_mosi; wire spi_miso; + wire tdd_enable_s; + wire gpio_enable; + wire gpio_txnrx; + wire enable_s; + wire txnrx_s; + // assignments assign fan_pwm = 1'b1; assign iic_rstn = 1'b1; assign spi_csn_0 = spi_csn[0]; + assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable; + assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx; + // instantiations ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( @@ -278,7 +289,10 @@ module system_top ( .tx_frame_out_n (tx_frame_out_n), .tx_frame_out_p (tx_frame_out_p), .uart_sin (uart_sin), - .uart_sout (uart_sout)); + .uart_sout (uart_sout), + .enable (enable_s), + .txnrx (txnrx_s), + .tdd_enable (tdd_enable_s)); endmodule diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 4a4f0a672..937f82781 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -1,177 +1,177 @@ - -# fmcomms2 - -create_bd_port -dir I rx_clk_in_p -create_bd_port -dir I rx_clk_in_n -create_bd_port -dir I rx_frame_in_p -create_bd_port -dir I rx_frame_in_n -create_bd_port -dir I -from 5 -to 0 rx_data_in_p -create_bd_port -dir I -from 5 -to 0 rx_data_in_n - -create_bd_port -dir O tx_clk_out_p -create_bd_port -dir O tx_clk_out_n -create_bd_port -dir O tx_frame_out_p -create_bd_port -dir O tx_frame_out_n -create_bd_port -dir O -from 5 -to 0 tx_data_out_p -create_bd_port -dir O -from 5 -to 0 tx_data_out_n - -create_bd_port -dir O enable -create_bd_port -dir O txnrx - -# ad9361 core - -set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9361 - -set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma - -set util_dac_unpack [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack] -set_property -dict [list CONFIG.CHANNELS {4}] $util_dac_unpack - -set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma - -set util_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack] -set_property -dict [list CONFIG.CHANNELS {4}] $util_adc_pack - -# connections - -ad_connect sys_200m_clk axi_ad9361/delay_clk -ad_connect axi_ad9361_clk axi_ad9361/l_clk -ad_connect axi_ad9361_clk axi_ad9361/clk -ad_connect axi_ad9361_clk axi_ad9361_adc_dma/fifo_wr_clk -ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk -ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p -ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n -ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p -ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n -ad_connect rx_data_in_p axi_ad9361/rx_data_in_p -ad_connect rx_data_in_n axi_ad9361/rx_data_in_n -ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p -ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n -ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p -ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n -ad_connect tx_data_out_p axi_ad9361/tx_data_out_p -ad_connect tx_data_out_n axi_ad9361/tx_data_out_n -ad_connect enable axi_ad9361/enable -ad_connect txnrx axi_ad9361/txnrx -ad_connect axi_ad9361_clk util_adc_pack/clk -ad_connect axi_ad9361/adc_valid_i0 util_adc_pack/chan_valid_0 -ad_connect axi_ad9361/adc_valid_q0 util_adc_pack/chan_valid_1 -ad_connect axi_ad9361/adc_valid_i1 util_adc_pack/chan_valid_2 -ad_connect axi_ad9361/adc_valid_q1 util_adc_pack/chan_valid_3 -ad_connect axi_ad9361/adc_enable_i0 util_adc_pack/chan_enable_0 -ad_connect axi_ad9361/adc_enable_q0 util_adc_pack/chan_enable_1 -ad_connect axi_ad9361/adc_enable_i1 util_adc_pack/chan_enable_2 -ad_connect axi_ad9361/adc_enable_q1 util_adc_pack/chan_enable_3 -ad_connect axi_ad9361/adc_data_i0 util_adc_pack/chan_data_0 -ad_connect axi_ad9361/adc_data_q0 util_adc_pack/chan_data_1 -ad_connect axi_ad9361/adc_data_i1 util_adc_pack/chan_data_2 -ad_connect axi_ad9361/adc_data_q1 util_adc_pack/chan_data_3 -ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn -ad_connect util_adc_pack/dvalid axi_ad9361_adc_dma/fifo_wr_en -ad_connect util_adc_pack/dsync axi_ad9361_adc_dma/fifo_wr_sync -ad_connect util_adc_pack/ddata axi_ad9361_adc_dma/fifo_wr_din -ad_connect axi_ad9361/adc_dovf axi_ad9361_adc_dma/fifo_wr_overflow -ad_connect axi_ad9361_clk util_dac_unpack/clk -ad_connect util_dac_unpack/dac_valid_00 axi_ad9361/dac_valid_i0 -ad_connect util_dac_unpack/dac_valid_01 axi_ad9361/dac_valid_q0 -ad_connect util_dac_unpack/dac_valid_02 axi_ad9361/dac_valid_i1 -ad_connect util_dac_unpack/dac_valid_03 axi_ad9361/dac_valid_q1 -ad_connect util_dac_unpack/dac_enable_00 axi_ad9361/dac_enable_i0 -ad_connect util_dac_unpack/dac_enable_01 axi_ad9361/dac_enable_q0 -ad_connect util_dac_unpack/dac_enable_02 axi_ad9361/dac_enable_i1 -ad_connect util_dac_unpack/dac_enable_03 axi_ad9361/dac_enable_q1 -ad_connect util_dac_unpack/dac_data_00 axi_ad9361/dac_data_i0 -ad_connect util_dac_unpack/dac_data_01 axi_ad9361/dac_data_q0 -ad_connect util_dac_unpack/dac_data_02 axi_ad9361/dac_data_i1 -ad_connect util_dac_unpack/dac_data_03 axi_ad9361/dac_data_q1 -ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn -ad_connect util_dac_unpack/dma_data axi_ad9361_dac_dma/fifo_rd_dout -ad_connect util_dac_unpack/fifo_valid axi_ad9361_dac_dma/fifo_rd_valid -ad_connect util_dac_unpack/dma_rd axi_ad9361_dac_dma/fifo_rd_en -ad_connect axi_ad9361/dac_dunf axi_ad9361_dac_dma/fifo_rd_underflow - -# interconnects - -ad_cpu_interconnect 0x79020000 axi_ad9361 -ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma -ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma -ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi -ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi - -# interrupts - -ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq -ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq - -# ila (adc) - -set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc -set_property -dict [list CONFIG.C_NUM_OF_PROBES {8}] $ila_adc -set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc -set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc -set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_adc -set_property -dict [list CONFIG.C_PROBE2_WIDTH {1}] $ila_adc -set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_adc -set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE5_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE6_WIDTH {16}] $ila_adc -set_property -dict [list CONFIG.C_PROBE7_WIDTH {16}] $ila_adc - -p_sys_wfifo [current_bd_instance .] sys_wfifo_0 16 16 -p_sys_wfifo [current_bd_instance .] sys_wfifo_1 16 16 -p_sys_wfifo [current_bd_instance .] sys_wfifo_2 16 16 -p_sys_wfifo [current_bd_instance .] sys_wfifo_3 16 16 - -ad_connect axi_ad9361_clk sys_wfifo_0/adc_clk -ad_connect axi_ad9361_clk sys_wfifo_1/adc_clk -ad_connect axi_ad9361_clk sys_wfifo_2/adc_clk -ad_connect axi_ad9361_clk sys_wfifo_3/adc_clk -ad_connect sys_wfifo_0/adc_wr axi_ad9361/adc_valid_i0 -ad_connect sys_wfifo_1/adc_wr axi_ad9361/adc_valid_q0 -ad_connect sys_wfifo_2/adc_wr axi_ad9361/adc_valid_i1 -ad_connect sys_wfifo_3/adc_wr axi_ad9361/adc_valid_q1 -ad_connect sys_wfifo_0/adc_wdata axi_ad9361/adc_data_i0 -ad_connect sys_wfifo_1/adc_wdata axi_ad9361/adc_data_q0 -ad_connect sys_wfifo_2/adc_wdata axi_ad9361/adc_data_i1 -ad_connect sys_wfifo_3/adc_wdata axi_ad9361/adc_data_q1 -ad_connect sys_cpu_clk ila_adc/clk -ad_connect sys_cpu_clk sys_wfifo_0/dma_clk -ad_connect sys_cpu_clk sys_wfifo_1/dma_clk -ad_connect sys_cpu_clk sys_wfifo_2/dma_clk -ad_connect sys_cpu_clk sys_wfifo_3/dma_clk -ad_connect sys_wfifo_0/dma_wr ila_adc/probe0 -ad_connect sys_wfifo_1/dma_wr ila_adc/probe1 -ad_connect sys_wfifo_2/dma_wr ila_adc/probe2 -ad_connect sys_wfifo_3/dma_wr ila_adc/probe3 -ad_connect sys_wfifo_0/dma_wdata ila_adc/probe4 -ad_connect sys_wfifo_1/dma_wdata ila_adc/probe5 -ad_connect sys_wfifo_2/dma_wdata ila_adc/probe6 -ad_connect sys_wfifo_3/dma_wdata ila_adc/probe7 - + +# fmcomms2 + +create_bd_port -dir I rx_clk_in_p +create_bd_port -dir I rx_clk_in_n +create_bd_port -dir I rx_frame_in_p +create_bd_port -dir I rx_frame_in_n +create_bd_port -dir I -from 5 -to 0 rx_data_in_p +create_bd_port -dir I -from 5 -to 0 rx_data_in_n + +create_bd_port -dir O tx_clk_out_p +create_bd_port -dir O tx_clk_out_n +create_bd_port -dir O tx_frame_out_p +create_bd_port -dir O tx_frame_out_n +create_bd_port -dir O -from 5 -to 0 tx_data_out_p +create_bd_port -dir O -from 5 -to 0 tx_data_out_n + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir O tdd_enable + +# ad9361 core + +set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] +set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9361 + +set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma + +set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack] +set_property -dict [list CONFIG.CH_CNT {4}] $util_ad9361_dac_upack +set_property -dict [list CONFIG.CH_DW {16}] $util_ad9361_dac_upack + +set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma + +set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack] +set_property -dict [list CONFIG.CH_CNT {4}] $util_ad9361_adc_pack +set_property -dict [list CONFIG.CH_DW {16}] $util_ad9361_adc_pack + +set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo +set_property -dict [list CONFIG.DIN_ADDR_WIDTH {4}] $util_ad9361_adc_fifo +set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo +set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo + +# connections + +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361_clk axi_ad9361/l_clk +ad_connect axi_ad9361_clk axi_ad9361/clk +ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p +ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n +ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p +ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n +ad_connect rx_data_in_p axi_ad9361/rx_data_in_p +ad_connect rx_data_in_n axi_ad9361/rx_data_in_n +ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p +ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n +ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p +ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n +ad_connect tx_data_out_p axi_ad9361/tx_data_out_p +ad_connect tx_data_out_n axi_ad9361/tx_data_out_n +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk +ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst +ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk +ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn +ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk +ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst +ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk +ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 +ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 +ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 +ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 +ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 +ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 +ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 +ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 +ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 +ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 +ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 +ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 +ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 +ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 +ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0 +ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 +ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 +ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1 +ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 +ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 +ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 +ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 +ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3 +ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3 +ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en +ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync +ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf +ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf +ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk +ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk +ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0 +ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0 +ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0 +ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0 +ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0 +ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0 +ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1 +ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1 +ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1 +ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1 +ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1 +ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1 +ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en +ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout +ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf +ad_connect tdd_enable axi_ad9361/tdd_enable + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq + +# ila (adc) + +set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc] +set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc +set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc +set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc +set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc +set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc +set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc +set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc +set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc +set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_adc + +ad_connect util_ad9361_adc_fifo/dout_data_0 ila_adc/probe0 +ad_connect util_ad9361_adc_fifo/dout_data_1 ila_adc/probe1 +ad_connect util_ad9361_adc_fifo/dout_data_2 ila_adc/probe2 +ad_connect util_ad9361_adc_fifo/dout_data_3 ila_adc/probe3 +ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_adc/probe4 +ad_connect sys_cpu_clk ila_adc/clk + diff --git a/projects/fmcomms2/kc705/system_constr.xdc b/projects/fmcomms2/kc705/system_constr.xdc index f403be1e4..11f60f7a6 100644 --- a/projects/fmcomms2/kc705/system_constr.xdc +++ b/projects/fmcomms2/kc705/system_constr.xdc @@ -1,39 +1,39 @@ # constraints -# ad9361 +# ad9361 -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AE24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN AF21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN AH20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN AH25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN AJ22 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN AK23 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN AK24 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN AC25 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AE24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN AF21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN AH20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN AH25 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN AJ22 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN AK23 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN AK24 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN AC25 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N set_property -dict {PACKAGE_PIN AF26 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N @@ -50,13 +50,14 @@ set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N -set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N + +set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N # clocks diff --git a/projects/fmcomms2/kc705/system_top.v b/projects/fmcomms2/kc705/system_top.v index b8c06a983..b97593a67 100644 --- a/projects/fmcomms2/kc705/system_top.v +++ b/projects/fmcomms2/kc705/system_top.v @@ -109,8 +109,9 @@ module system_top ( tx_data_out_p, tx_data_out_n, - gpio_txnrx, - gpio_enable, + txnrx, + enable, + gpio_resetb, gpio_sync, gpio_en_agc, @@ -191,8 +192,9 @@ module system_top ( output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_n; - inout gpio_txnrx; - inout gpio_enable; + output txnrx; + output enable; + inout gpio_resetb; inout gpio_sync; inout gpio_en_agc; @@ -214,6 +216,12 @@ module system_top ( wire spi_mosi; wire spi_miso; + wire tdd_enable_s; + wire gpio_enable; + wire gpio_txnrx; + wire enable_s; + wire txnrx_s; + // default logic assign ddr3_1_p = 2'b11; @@ -222,12 +230,15 @@ module system_top ( assign iic_rstn = 1'b1; assign spi_csn_0 = spi_csn[0]; + assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable; + assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx; + // instantiations ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( - .dio_t (gpio_t[49:32]), - .dio_i (gpio_o[49:32]), - .dio_o (gpio_i[49:32]), + .dio_t (gpio_t[48:32]), + .dio_i (gpio_o[48:32]), + .dio_o (gpio_i[48:32]), .dio_p ({ gpio_txnrx, gpio_enable, gpio_resetb, @@ -314,7 +325,10 @@ module system_top ( .tx_frame_out_n (tx_frame_out_n), .tx_frame_out_p (tx_frame_out_p), .uart_sin (uart_sin), - .uart_sout (uart_sout)); + .uart_sout (uart_sout), + .enable (enable_s), + .txnrx (txnrx_s), + .tdd_enable (tdd_enable_s)); endmodule diff --git a/projects/fmcomms2/mitx045/system_constr.xdc b/projects/fmcomms2/mitx045/system_constr.xdc index 8797f68b9..d10448e56 100644 --- a/projects/fmcomms2/mitx045/system_constr.xdc +++ b/projects/fmcomms2/mitx045/system_constr.xdc @@ -1,64 +1,65 @@ - -# constraints -# ad9361 - -set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N - -set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P -set_property -dict {PACKAGE_PIN AK12 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N -set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P -set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N -set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P -set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N -set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P -set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N -set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N -set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P -set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N -set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N - -set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N - -# clocks - -create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p] -create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] + +# constraints +# ad9361 + +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N + +set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN AK12 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N +set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N + +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N + +# clocks + +create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p] +create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] + diff --git a/projects/fmcomms2/mitx045/system_top.v b/projects/fmcomms2/mitx045/system_top.v index eef209f3f..c5e5a7dba 100644 --- a/projects/fmcomms2/mitx045/system_top.v +++ b/projects/fmcomms2/mitx045/system_top.v @@ -1,290 +1,304 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, - - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, - - gpio_bd, - - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, - - spdif, - - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, - - iic_scl, - iic_sda, - - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, - - gpio_txnrx, - gpio_enable, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, - - spi_csn, - spi_clk, - spi_mosi, - spi_miso); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [11:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - inout iic_scl; - inout iic_sda; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - - inout gpio_txnrx; - inout gpio_enable; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( - .dio_t (gpio_t[48:32]), - .dio_i (gpio_o[48:32]), - .dio_o (gpio_i[48:32]), - .dio_p ({ gpio_txnrx, - gpio_enable, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status})); - - ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( - .dio_t (gpio_t[11:0]), - .dio_i (gpio_o[11:0]), - .dio_o (gpio_i[11:0]), - .dio_p (gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .i2s_bclk (i2s_bclk), - .i2s_lrclk (i2s_lrclk), - .i2s_mclk (i2s_mclk), - .i2s_sdata_in (i2s_sdata_in), - .i2s_sdata_out (i2s_sdata_out), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_10 (1'b0), - .ps_intr_11 (1'b0), - .rx_clk_in_n (rx_clk_in_n), - .rx_clk_in_p (rx_clk_in_p), - .rx_data_in_n (rx_data_in_n), - .rx_data_in_p (rx_data_in_p), - .rx_frame_in_n (rx_frame_in_n), - .rx_frame_in_p (rx_frame_in_p), - .spdif (spdif), - .spi0_clk_i (1'b0), - .spi0_clk_o (spi_clk), - .spi0_csn_0_o (spi_csn), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi_miso), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (spi_mosi), - .spi1_clk_i (1'b0), - .spi1_clk_o (), - .spi1_csn_0_o (), - .spi1_csn_1_o (), - .spi1_csn_2_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (), - .spi1_sdo_o (), - .tx_clk_out_n (tx_clk_out_n), - .tx_clk_out_p (tx_clk_out_p), - .tx_data_out_n (tx_data_out_n), - .tx_data_out_p (tx_data_out_p), - .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p)); - -endmodule - -// *************************************************************************** -// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + + iic_scl, + iic_sda, + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + + txnrx, + enable, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout [11:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + output spdif; + + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; + + inout iic_scl; + inout iic_sda; + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + + output txnrx; + output enable; + inout gpio_resetb; + inout gpio_sync; + inout gpio_en_agc; + inout [ 3:0] gpio_ctl; + inout [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire tdd_enable_s; + wire gpio_enable; + wire gpio_txnrx; + wire enable_s; + wire txnrx_s; + + // assignments + + assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable; + assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( + .dio_t (gpio_t[48:32]), + .dio_i (gpio_o[48:32]), + .dio_o (gpio_i[48:32]), + .dio_p ({ gpio_txnrx, + gpio_enable, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status})); + + ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( + .dio_t (gpio_t[11:0]), + .dio_i (gpio_o[11:0]), + .dio_o (gpio_i[11:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (), + .spi1_sdo_o (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .enable (enable_s), + .txnrx (txnrx_s), + .tdd_enable (tdd_enable_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms2/rfsom/system_top.v b/projects/fmcomms2/rfsom/system_top.v index ffd6ab1e6..dff0499b9 100644 --- a/projects/fmcomms2/rfsom/system_top.v +++ b/projects/fmcomms2/rfsom/system_top.v @@ -1,344 +1,355 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, - - eth1_mdc, - eth1_mdio, - eth1_rgmii_rxclk, - eth1_rgmii_rxctl, - eth1_rgmii_rxdata, - eth1_rgmii_txclk, - eth1_rgmii_txctl, - eth1_rgmii_txdata, - - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, - - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, - hdmi_pd, - hdmi_intn, - - spdif, - spdif_in, - - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, - - iic_scl, - iic_sda, - - gpio_bd, - - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, - enable, - txnrx, - - gpio_rfpwr_enable, - gpio_clksel, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, - - spi_csn, - spi_clk, - spi_mosi, - spi_miso); - - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - output eth1_mdc; - inout eth1_mdio; - input eth1_rgmii_rxclk; - input eth1_rgmii_rxctl; - input [ 3:0] eth1_rgmii_rxdata; - output eth1_rgmii_txclk; - output eth1_rgmii_txctl; - output [ 3:0] eth1_rgmii_txdata; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - output hdmi_pd; - input hdmi_intn; - - output spdif; - input spdif_in; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - inout iic_scl; - inout iic_sda; - - inout [11:0] gpio_bd; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - output enable; - output txnrx; - - inout gpio_rfpwr_enable; - inout gpio_clksel; - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - - // assignments - - assign hdmi_pd = 1'b0; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( - .dio_t ({gpio_t[50:49], gpio_t[46:32]}), - .dio_i ({gpio_o[50:49], gpio_o[46:32]}), - .dio_o ({gpio_i[50:49], gpio_i[46:32]}), - .dio_p ({ gpio_rfpwr_enable, - gpio_clksel, - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status})); - - ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( - .dio_t (gpio_t[11:0]), - .dio_i (gpio_o[11:0]), - .dio_o (gpio_i[11:0]), - .dio_p (gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .enable (enable), - .eth1_125mclk (), - .eth1_25mclk (), - .eth1_2m5clk (), - .eth1_clock_speed (), - .eth1_duplex_status (), - .eth1_intn (1'b1), - .eth1_link_status (), - .eth1_mdio_mdc (eth1_mdc), - .eth1_mdio_mdio_io (eth1_mdio), - .eth1_refclk (), - .eth1_rgmii_rd (eth1_rgmii_rxdata), - .eth1_rgmii_rx_ctl (eth1_rgmii_rxctl), - .eth1_rgmii_rxc (eth1_rgmii_rxclk), - .eth1_rgmii_td (eth1_rgmii_txdata), - .eth1_rgmii_tx_ctl (eth1_rgmii_txctl), - .eth1_rgmii_txc (eth1_rgmii_txclk), - .eth1_speed_mode (), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .i2s_bclk (i2s_bclk), - .i2s_lrclk (i2s_lrclk), - .i2s_mclk (i2s_mclk), - .i2s_sdata_in (i2s_sdata_in), - .i2s_sdata_out (i2s_sdata_out), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .otg_vbusoc (1'b0), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_10 (1'b0), - .ps_intr_11 (1'b0), - .rx_clk_in_n (rx_clk_in_n), - .rx_clk_in_p (rx_clk_in_p), - .rx_data_in_n (rx_data_in_n), - .rx_data_in_p (rx_data_in_p), - .rx_frame_in_n (rx_frame_in_n), - .rx_frame_in_p (rx_frame_in_p), - .spdif (spdif), - .spi0_clk_i (1'b0), - .spi0_clk_o (spi_clk), - .spi0_csn_0_o (spi_csn), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi_miso), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (spi_mosi), - .spi1_clk_i (1'b0), - .spi1_clk_o (), - .spi1_csn_0_o (), - .spi1_csn_1_o (), - .spi1_csn_2_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (1'b0), - .spi1_sdo_o (), - .tx_clk_out_n (tx_clk_out_n), - .tx_clk_out_p (tx_clk_out_p), - .tx_data_out_n (tx_data_out_n), - .tx_data_out_p (tx_data_out_p), - .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p), - .txnrx (txnrx)); - -endmodule - -// *************************************************************************** -// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + eth1_mdc, + eth1_mdio, + eth1_rgmii_rxclk, + eth1_rgmii_rxctl, + eth1_rgmii_rxdata, + eth1_rgmii_txclk, + eth1_rgmii_txctl, + eth1_rgmii_txdata, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + hdmi_pd, + hdmi_intn, + + spdif, + spdif_in, + + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + + iic_scl, + iic_sda, + + gpio_bd, + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + enable, + txnrx, + + gpio_rfpwr_enable, + gpio_clksel, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + output eth1_mdc; + inout eth1_mdio; + input eth1_rgmii_rxclk; + input eth1_rgmii_rxctl; + input [ 3:0] eth1_rgmii_rxdata; + output eth1_rgmii_txclk; + output eth1_rgmii_txctl; + output [ 3:0] eth1_rgmii_txdata; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [15:0] hdmi_data; + output hdmi_pd; + input hdmi_intn; + + output spdif; + input spdif_in; + + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; + + inout iic_scl; + inout iic_sda; + + inout [11:0] gpio_bd; + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + output enable; + output txnrx; + + inout gpio_rfpwr_enable; + inout gpio_clksel; + inout gpio_resetb; + inout gpio_sync; + inout gpio_en_agc; + inout [ 3:0] gpio_ctl; + inout [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire tdd_enable_s; + wire gpio_enable; + wire gpio_txnrx; + wire enable_s; + wire txnrx_s; + + // assignments + + assign hdmi_pd = 1'b0; + assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable; + assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(19)) i_iobuf ( + .dio_t ({gpio_t[51:50], gpio_t[48:32]}), + .dio_i ({gpio_o[51:50], gpio_o[48:32]}), + .dio_o ({gpio_i[51:50], gpio_i[48:32]}), + .dio_p ({ gpio_rfpwr_enable, + gpio_clksel, + gpio_txnrx, + gpio_enable, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status})); + + ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( + .dio_t (gpio_t[11:0]), + .dio_i (gpio_o[11:0]), + .dio_o (gpio_i[11:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable_s), + .eth1_125mclk (), + .eth1_25mclk (), + .eth1_2m5clk (), + .eth1_clock_speed (), + .eth1_duplex_status (), + .eth1_intn (1'b1), + .eth1_link_status (), + .eth1_mdio_mdc (eth1_mdc), + .eth1_mdio_mdio_io (eth1_mdio), + .eth1_refclk (), + .eth1_rgmii_rd (eth1_rgmii_rxdata), + .eth1_rgmii_rx_ctl (eth1_rgmii_rxctl), + .eth1_rgmii_rxc (eth1_rgmii_rxclk), + .eth1_rgmii_td (eth1_rgmii_txdata), + .eth1_rgmii_tx_ctl (eth1_rgmii_txctl), + .eth1_rgmii_txc (eth1_rgmii_txclk), + .eth1_speed_mode (), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx_s), + .tdd_enable (tdd_enable_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms2/vc707/system_constr.xdc b/projects/fmcomms2/vc707/system_constr.xdc index 675091e67..0055cd205 100644 --- a/projects/fmcomms2/vc707/system_constr.xdc +++ b/projects/fmcomms2/vc707/system_constr.xdc @@ -1,39 +1,39 @@ # constraints -# ad9361 +# ad9361 -set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN P42 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN F41 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN G39 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN M39 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN N39 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN N40 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN M36 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN L37 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N +set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVDS} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVDS} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN R42 IOSTANDARD LVDS} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN P42 IOSTANDARD LVDS} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN F40 IOSTANDARD LVDS} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN F41 IOSTANDARD LVDS} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN R40 IOSTANDARD LVDS} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN P40 IOSTANDARD LVDS} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN H39 IOSTANDARD LVDS} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN G39 IOSTANDARD LVDS} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVDS} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN M39 IOSTANDARD LVDS} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN N39 IOSTANDARD LVDS} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN N40 IOSTANDARD LVDS} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN M36 IOSTANDARD LVDS} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN L37 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N @@ -50,13 +50,13 @@ set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[ set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN W31 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N +set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N -set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN J31 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN H31 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N +set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN J31 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN H31 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N # clocks diff --git a/projects/fmcomms2/vc707/system_top.v b/projects/fmcomms2/vc707/system_top.v index 943099641..641a8b409 100644 --- a/projects/fmcomms2/vc707/system_top.v +++ b/projects/fmcomms2/vc707/system_top.v @@ -104,8 +104,9 @@ module system_top ( tx_data_out_p, tx_data_out_n, - gpio_txnrx, - gpio_enable, + txnrx, + enable, + gpio_resetb, gpio_sync, gpio_en_agc, @@ -183,8 +184,8 @@ module system_top ( output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_n; - inout gpio_txnrx; - inout gpio_enable; + output txnrx; + output enable; inout gpio_resetb; inout gpio_sync; inout gpio_en_agc; @@ -206,12 +207,21 @@ module system_top ( wire spi_mosi; wire spi_miso; + wire tdd_enable_s; + wire gpio_enable; + wire gpio_txnrx; + wire enable_s; + wire txnrx_s; + // default logic assign fan_pwm = 1'b1; assign iic_rstn = 1'b1; assign spi_csn_0 = spi_csn[0]; + assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable; + assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx; + // instantiations ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( @@ -301,7 +311,10 @@ module system_top ( .tx_frame_out_n (tx_frame_out_n), .tx_frame_out_p (tx_frame_out_p), .uart_sin (uart_sin), - .uart_sout (uart_sout)); + .uart_sout (uart_sout), + .enable (enable_s), + .txnrx (txnrx_s), + .tdd_enable (tdd_enable_s)); endmodule diff --git a/projects/fmcomms2/zc702/system_constr.xdc b/projects/fmcomms2/zc702/system_constr.xdc index 922a29d46..3a4563964 100644 --- a/projects/fmcomms2/zc702/system_constr.xdc +++ b/projects/fmcomms2/zc702/system_constr.xdc @@ -1,39 +1,39 @@ # constraints -# ad9361 +# ad9361 -set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N @@ -50,13 +50,13 @@ set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[ set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N # clocks diff --git a/projects/fmcomms2/zc702/system_top.v b/projects/fmcomms2/zc702/system_top.v index 24b9d747a..de46e4c6b 100644 --- a/projects/fmcomms2/zc702/system_top.v +++ b/projects/fmcomms2/zc702/system_top.v @@ -90,8 +90,9 @@ module system_top ( tx_data_out_p, tx_data_out_n, - gpio_txnrx, - gpio_enable, + txnrx, + enable, + gpio_resetb, gpio_sync, gpio_en_agc, @@ -152,8 +153,8 @@ module system_top ( output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_n; - inout gpio_txnrx; - inout gpio_enable; + output txnrx; + output enable; inout gpio_resetb; inout gpio_sync; inout gpio_en_agc; @@ -176,6 +177,17 @@ module system_top ( wire spi_udc_sclk; wire spi_udc_data; + wire tdd_enable_s; + wire gpio_enable; + wire gpio_txnrx; + wire enable_s; + wire txnrx_s; + + // internal logic + + assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable; + assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx; + // instantiations ad_iobuf #(.DATA_WIDTH(29)) i_iobuf ( @@ -273,7 +285,10 @@ module system_top ( .spi1_csn_2_o(), .spi1_sdo_i (spi_udc_data), .spi1_sdo_o (spi_udc_data), - .spi1_sdi_i (1'b0)); + .spi1_sdi_i (1'b0), + .enable (enable_s), + .txnrx (txnrx_s), + .tdd_enable (tdd_enable_s)); endmodule diff --git a/projects/fmcomms2/zc706/system_top.v b/projects/fmcomms2/zc706/system_top.v index a985c1fee..3cb6682fc 100644 --- a/projects/fmcomms2/zc706/system_top.v +++ b/projects/fmcomms2/zc706/system_top.v @@ -1,304 +1,318 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - ddr_addr, - ddr_ba, - ddr_cas_n, - ddr_ck_n, - ddr_ck_p, - ddr_cke, - ddr_cs_n, - ddr_dm, - ddr_dq, - ddr_dqs_n, - ddr_dqs_p, - ddr_odt, - ddr_ras_n, - ddr_reset_n, - ddr_we_n, - - fixed_io_ddr_vrn, - fixed_io_ddr_vrp, - fixed_io_mio, - fixed_io_ps_clk, - fixed_io_ps_porb, - fixed_io_ps_srstb, - - gpio_bd, - - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, - - spdif, - - iic_scl, - iic_sda, - - rx_clk_in_p, - rx_clk_in_n, - rx_frame_in_p, - rx_frame_in_n, - rx_data_in_p, - rx_data_in_n, - tx_clk_out_p, - tx_clk_out_n, - tx_frame_out_p, - tx_frame_out_n, - tx_data_out_p, - tx_data_out_n, - enable, - txnrx, - - gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status, - - spi_csn, - spi_clk, - spi_mosi, - spi_miso, - - spi_udc_csn_tx, - spi_udc_csn_rx, - spi_udc_sclk, - spi_udc_data); - - inout [14:0] ddr_addr; - inout [ 2:0] ddr_ba; - inout ddr_cas_n; - inout ddr_ck_n; - inout ddr_ck_p; - inout ddr_cke; - inout ddr_cs_n; - inout [ 3:0] ddr_dm; - inout [31:0] ddr_dq; - inout [ 3:0] ddr_dqs_n; - inout [ 3:0] ddr_dqs_p; - inout ddr_odt; - inout ddr_ras_n; - inout ddr_reset_n; - inout ddr_we_n; - - inout fixed_io_ddr_vrn; - inout fixed_io_ddr_vrp; - inout [53:0] fixed_io_mio; - inout fixed_io_ps_clk; - inout fixed_io_ps_porb; - inout fixed_io_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input rx_clk_in_p; - input rx_clk_in_n; - input rx_frame_in_p; - input rx_frame_in_n; - input [ 5:0] rx_data_in_p; - input [ 5:0] rx_data_in_n; - output tx_clk_out_p; - output tx_clk_out_n; - output tx_frame_out_p; - output tx_frame_out_n; - output [ 5:0] tx_data_out_p; - output [ 5:0] tx_data_out_n; - output enable; - output txnrx; - - inout gpio_resetb; - inout gpio_sync; - inout gpio_en_agc; - inout [ 3:0] gpio_ctl; - inout [ 7:0] gpio_status; - - output spi_csn; - output spi_clk; - output spi_mosi; - input spi_miso; - - output spi_udc_csn_tx; - output spi_udc_csn_rx; - output spi_udc_sclk; - output spi_udc_data; - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire clk; - wire dma_dac_dunf; - wire core_dac_dunf; - wire [63:0] dma_dac_ddata; - wire [63:0] core_dac_ddata; - wire dma_dac_en; - wire core_dac_en; - wire dma_dac_dvalid; - wire core_dac_dvalid; - wire dma_adc_ovf; - wire core_adc_ovf; - wire [63:0] dma_adc_ddata; - wire [63:0] core_adc_ddata; - wire dma_adc_dwr; - wire core_adc_dwr; - wire dma_adc_dsync; - wire core_adc_dsync; - wire [31:0] adc_gpio_input; - wire [31:0] adc_gpio_output; - wire [31:0] dac_gpio_input; - wire [31:0] dac_gpio_output; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(15)) i_iobuf ( - .dio_t (gpio_t[46:32]), - .dio_i (gpio_o[46:32]), - .dio_o (gpio_i[46:32]), - .dio_p ({ gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status})); - - ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( - .dio_t (gpio_t[14:0]), - .dio_i (gpio_o[14:0]), - .dio_o (gpio_i[14:0]), - .dio_p (gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .enable (enable), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_10 (1'b0), - .ps_intr_11 (1'b0), - .rx_clk_in_n (rx_clk_in_n), - .rx_clk_in_p (rx_clk_in_p), - .rx_data_in_n (rx_data_in_n), - .rx_data_in_p (rx_data_in_p), - .rx_frame_in_n (rx_frame_in_n), - .rx_frame_in_p (rx_frame_in_p), - .spdif (spdif), - .spi0_clk_i (1'b0), - .spi0_clk_o (spi_clk), - .spi0_csn_0_o (spi_csn), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi_miso), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (spi_mosi), - .spi1_clk_i (1'b0), - .spi1_clk_o (spi_udc_sclk), - .spi1_csn_0_o (spi_udc_csn_tx), - .spi1_csn_1_o (spi_udc_csn_rx), - .spi1_csn_2_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (spi_udc_data), - .spi1_sdo_o (spi_udc_data), - .tx_clk_out_n (tx_clk_out_n), - .tx_clk_out_p (tx_clk_out_p), - .tx_data_out_n (tx_data_out_n), - .tx_data_out_p (tx_data_out_p), - .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p), - .txnrx (txnrx)); - -endmodule - -// *************************************************************************** -// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + + enable, + txnrx, + + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso, + + spi_udc_csn_tx, + spi_udc_csn_rx, + spi_udc_sclk, + spi_udc_data); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + + output enable; + output txnrx; + + inout gpio_resetb; + inout gpio_sync; + inout gpio_en_agc; + inout [ 3:0] gpio_ctl; + inout [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + output spi_udc_csn_tx; + output spi_udc_csn_rx; + output spi_udc_sclk; + output spi_udc_data; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire clk; + wire dma_dac_dunf; + wire core_dac_dunf; + wire [63:0] dma_dac_ddata; + wire [63:0] core_dac_ddata; + wire dma_dac_en; + wire core_dac_en; + wire dma_dac_dvalid; + wire core_dac_dvalid; + wire dma_adc_ovf; + wire core_adc_ovf; + wire [63:0] dma_adc_ddata; + wire [63:0] core_adc_ddata; + wire dma_adc_dwr; + wire core_adc_dwr; + wire dma_adc_dsync; + wire core_adc_dsync; + wire [31:0] adc_gpio_input; + wire [31:0] adc_gpio_output; + wire [31:0] dac_gpio_input; + wire [31:0] dac_gpio_output; + + wire tdd_enable_s; + wire gpio_enable; + wire gpio_txnrx; + wire enable_s; + wire txnrx_s; + + assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable; + assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( + .dio_t (gpio_t[48:32]), + .dio_i (gpio_o[48:32]), + .dio_o (gpio_i[48:32]), + .dio_p ({ gpio_txnrx, + gpio_enable, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status})); + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p (gpio_bd)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable_s), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (spi_udc_sclk), + .spi1_csn_0_o (spi_udc_csn_tx), + .spi1_csn_1_o (spi_udc_csn_rx), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (spi_udc_data), + .spi1_sdo_o (spi_udc_data), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx_s), + .tdd_enable (tdd_enable_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms2/zed/system_constr.xdc b/projects/fmcomms2/zed/system_constr.xdc index 45c601ee0..58038d19b 100644 --- a/projects/fmcomms2/zed/system_constr.xdc +++ b/projects/fmcomms2/zed/system_constr.xdc @@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[ set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N diff --git a/projects/fmcomms2/zed/system_top.v b/projects/fmcomms2/zed/system_top.v index 49acf84ee..7e724b4b6 100644 --- a/projects/fmcomms2/zed/system_top.v +++ b/projects/fmcomms2/zed/system_top.v @@ -100,8 +100,9 @@ module system_top ( tx_data_out_p, tx_data_out_n, - gpio_txnrx, - gpio_enable, + txnrx, + enable, + gpio_resetb, gpio_sync, gpio_en_agc, @@ -177,8 +178,9 @@ module system_top ( output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_n; - inout gpio_txnrx; - inout gpio_enable; + output txnrx; + output enable; + inout gpio_resetb; inout gpio_sync; inout gpio_en_agc; @@ -207,6 +209,17 @@ module system_top ( wire [ 1:0] iic_mux_sda_o_s; wire iic_mux_sda_t_s; + wire tdd_enable_s; + wire gpio_enable; + wire gpio_txnrx; + wire enable_s; + wire txnrx_s; + + // internal logic + + assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable; + assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx; + // instantiations ad_iobuf #(.DATA_WIDTH(49)) i_iobuf_gpio ( @@ -319,7 +332,10 @@ module system_top ( .tx_data_out_n (tx_data_out_n), .tx_data_out_p (tx_data_out_p), .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p)); + .tx_frame_out_p (tx_frame_out_p), + .enable (enable_s), + .txnrx (txnrx_s), + .tdd_enable (tdd_enable_s)); endmodule