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fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control 

By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
main
Istvan Csomortani 2015-07-01 13:54:01 +03:00
parent 4744fca18e
commit 6b15704b70
15 changed files with 1479 additions and 1365 deletions
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5
projects/fmcomms2/ac701/system_constr.xdc
View File

@ -50,8 +50,9 @@ set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

24
projects/fmcomms2/ac701/system_top.v
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@ -97,8 +97,9 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -167,8 +168,9 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -190,12 +192,21 @@ module system_top (
wire spi_mosi;
wire spi_miso;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// assignments
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
assign spi_csn_0 = spi_csn[0];
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -278,7 +289,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
.uart_sout (uart_sout),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

160
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -17,6 +17,7 @@ create_bd_port -dir O -from 5 -to 0 tx_data_out_n
create_bd_port -dir O enable
create_bd_port -dir O txnrx
create_bd_port -dir O tdd_enable
# ad9361 core
@ -36,8 +37,9 @@ set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma
set util_dac_unpack [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack]
set_property -dict [list CONFIG.CHANNELS {4}] $util_dac_unpack
set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
set_property -dict [list CONFIG.CH_CNT {4}] $util_ad9361_dac_upack
set_property -dict [list CONFIG.CH_DW {16}] $util_ad9361_dac_upack
set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
@ -52,16 +54,21 @@ set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma
set util_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack]
set_property -dict [list CONFIG.CHANNELS {4}] $util_adc_pack
set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
set_property -dict [list CONFIG.CH_CNT {4}] $util_ad9361_adc_pack
set_property -dict [list CONFIG.CH_DW {16}] $util_ad9361_adc_pack
set util_ad9361_adc_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 util_ad9361_adc_fifo]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9361_adc_fifo
set_property -dict [list CONFIG.DIN_ADDR_WIDTH {4}] $util_ad9361_adc_fifo
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
# connections
ad_connect sys_200m_clk axi_ad9361/delay_clk
ad_connect axi_ad9361_clk axi_ad9361/l_clk
ad_connect axi_ad9361_clk axi_ad9361/clk
ad_connect axi_ad9361_clk axi_ad9361_adc_dma/fifo_wr_clk
ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
@ -76,42 +83,60 @@ ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
ad_connect enable axi_ad9361/enable
ad_connect txnrx axi_ad9361/txnrx
ad_connect axi_ad9361_clk util_adc_pack/clk
ad_connect axi_ad9361/adc_valid_i0 util_adc_pack/chan_valid_0
ad_connect axi_ad9361/adc_valid_q0 util_adc_pack/chan_valid_1
ad_connect axi_ad9361/adc_valid_i1 util_adc_pack/chan_valid_2
ad_connect axi_ad9361/adc_valid_q1 util_adc_pack/chan_valid_3
ad_connect axi_ad9361/adc_enable_i0 util_adc_pack/chan_enable_0
ad_connect axi_ad9361/adc_enable_q0 util_adc_pack/chan_enable_1
ad_connect axi_ad9361/adc_enable_i1 util_adc_pack/chan_enable_2
ad_connect axi_ad9361/adc_enable_q1 util_adc_pack/chan_enable_3
ad_connect axi_ad9361/adc_data_i0 util_adc_pack/chan_data_0
ad_connect axi_ad9361/adc_data_q0 util_adc_pack/chan_data_1
ad_connect axi_ad9361/adc_data_i1 util_adc_pack/chan_data_2
ad_connect axi_ad9361/adc_data_q1 util_adc_pack/chan_data_3
ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
ad_connect util_adc_pack/dvalid axi_ad9361_adc_dma/fifo_wr_en
ad_connect util_adc_pack/dsync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_adc_pack/ddata axi_ad9361_adc_dma/fifo_wr_din
ad_connect axi_ad9361/adc_dovf axi_ad9361_adc_dma/fifo_wr_overflow
ad_connect axi_ad9361_clk util_dac_unpack/clk
ad_connect util_dac_unpack/dac_valid_00 axi_ad9361/dac_valid_i0
ad_connect util_dac_unpack/dac_valid_01 axi_ad9361/dac_valid_q0
ad_connect util_dac_unpack/dac_valid_02 axi_ad9361/dac_valid_i1
ad_connect util_dac_unpack/dac_valid_03 axi_ad9361/dac_valid_q1
ad_connect util_dac_unpack/dac_enable_00 axi_ad9361/dac_enable_i0
ad_connect util_dac_unpack/dac_enable_01 axi_ad9361/dac_enable_q0
ad_connect util_dac_unpack/dac_enable_02 axi_ad9361/dac_enable_i1
ad_connect util_dac_unpack/dac_enable_03 axi_ad9361/dac_enable_q1
ad_connect util_dac_unpack/dac_data_00 axi_ad9361/dac_data_i0
ad_connect util_dac_unpack/dac_data_01 axi_ad9361/dac_data_q0
ad_connect util_dac_unpack/dac_data_02 axi_ad9361/dac_data_i1
ad_connect util_dac_unpack/dac_data_03 axi_ad9361/dac_data_q1
ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
ad_connect util_dac_unpack/dma_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect util_dac_unpack/fifo_valid axi_ad9361_dac_dma/fifo_rd_valid
ad_connect util_dac_unpack/dma_rd axi_ad9361_dac_dma/fifo_rd_en
ad_connect axi_ad9361/dac_dunf axi_ad9361_dac_dma/fifo_rd_underflow
ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk
ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn
ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk
ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst
ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk
ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk
ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
ad_connect tdd_enable axi_ad9361/tdd_enable
# interconnects
@ -122,6 +147,8 @@ ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
# interrupts
@ -132,46 +159,19 @@ ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
set_property -dict [list CONFIG.C_NUM_OF_PROBES {8}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_adc
set_property -dict [list CONFIG.C_PROBE2_WIDTH {1}] $ila_adc
set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_adc
set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE5_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE6_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE7_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc
set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_adc
p_sys_wfifo [current_bd_instance .] sys_wfifo_0 16 16
p_sys_wfifo [current_bd_instance .] sys_wfifo_1 16 16
p_sys_wfifo [current_bd_instance .] sys_wfifo_2 16 16
p_sys_wfifo [current_bd_instance .] sys_wfifo_3 16 16
ad_connect axi_ad9361_clk sys_wfifo_0/adc_clk
ad_connect axi_ad9361_clk sys_wfifo_1/adc_clk
ad_connect axi_ad9361_clk sys_wfifo_2/adc_clk
ad_connect axi_ad9361_clk sys_wfifo_3/adc_clk
ad_connect sys_wfifo_0/adc_wr axi_ad9361/adc_valid_i0
ad_connect sys_wfifo_1/adc_wr axi_ad9361/adc_valid_q0
ad_connect sys_wfifo_2/adc_wr axi_ad9361/adc_valid_i1
ad_connect sys_wfifo_3/adc_wr axi_ad9361/adc_valid_q1
ad_connect sys_wfifo_0/adc_wdata axi_ad9361/adc_data_i0
ad_connect sys_wfifo_1/adc_wdata axi_ad9361/adc_data_q0
ad_connect sys_wfifo_2/adc_wdata axi_ad9361/adc_data_i1
ad_connect sys_wfifo_3/adc_wdata axi_ad9361/adc_data_q1
ad_connect util_ad9361_adc_fifo/dout_data_0 ila_adc/probe0
ad_connect util_ad9361_adc_fifo/dout_data_1 ila_adc/probe1
ad_connect util_ad9361_adc_fifo/dout_data_2 ila_adc/probe2
ad_connect util_ad9361_adc_fifo/dout_data_3 ila_adc/probe3
ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_adc/probe4
ad_connect sys_cpu_clk ila_adc/clk
ad_connect sys_cpu_clk sys_wfifo_0/dma_clk
ad_connect sys_cpu_clk sys_wfifo_1/dma_clk
ad_connect sys_cpu_clk sys_wfifo_2/dma_clk
ad_connect sys_cpu_clk sys_wfifo_3/dma_clk
ad_connect sys_wfifo_0/dma_wr ila_adc/probe0
ad_connect sys_wfifo_1/dma_wr ila_adc/probe1
ad_connect sys_wfifo_2/dma_wr ila_adc/probe2
ad_connect sys_wfifo_3/dma_wr ila_adc/probe3
ad_connect sys_wfifo_0/dma_wdata ila_adc/probe4
ad_connect sys_wfifo_1/dma_wdata ila_adc/probe5
ad_connect sys_wfifo_2/dma_wdata ila_adc/probe6
ad_connect sys_wfifo_3/dma_wdata ila_adc/probe7

5
projects/fmcomms2/kc705/system_constr.xdc
View File

@ -50,8 +50,9 @@ set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports gpio_ctl
set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD22 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

30
projects/fmcomms2/kc705/system_top.v
View File

@ -109,8 +109,9 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -191,8 +192,9 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -214,6 +216,12 @@ module system_top (
wire spi_mosi;
wire spi_miso;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// default logic
assign ddr3_1_p = 2'b11;
@ -222,12 +230,15 @@ module system_top (
assign iic_rstn = 1'b1;
assign spi_csn_0 = spi_csn[0];
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dio_t (gpio_t[49:32]),
.dio_i (gpio_o[49:32]),
.dio_o (gpio_i[49:32]),
.dio_t (gpio_t[48:32]),
.dio_i (gpio_o[48:32]),
.dio_o (gpio_i[48:32]),
.dio_p ({ gpio_txnrx,
gpio_enable,
gpio_resetb,
@ -314,7 +325,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
.uart_sout (uart_sout),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

5
projects/fmcomms2/mitx045/system_constr.xdc
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@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N
@ -62,3 +62,4 @@ set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports spi_miso
create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p]
create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]

24
projects/fmcomms2/mitx045/system_top.v
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@ -96,8 +96,8 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -164,8 +164,8 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -183,6 +183,17 @@ module system_top (
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// assignments
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -282,7 +293,10 @@ module system_top (
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p));
.tx_frame_out_p (tx_frame_out_p),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

23
projects/fmcomms2/rfsom/system_top.v
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@ -213,18 +213,28 @@ module system_top (
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// assignments
assign hdmi_pd = 1'b0;
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dio_t ({gpio_t[50:49], gpio_t[46:32]}),
.dio_i ({gpio_o[50:49], gpio_o[46:32]}),
.dio_o ({gpio_i[50:49], gpio_i[46:32]}),
ad_iobuf #(.DATA_WIDTH(19)) i_iobuf (
.dio_t ({gpio_t[51:50], gpio_t[48:32]}),
.dio_i ({gpio_o[51:50], gpio_o[48:32]}),
.dio_o ({gpio_i[51:50], gpio_i[48:32]}),
.dio_p ({ gpio_rfpwr_enable,
gpio_clksel,
gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -253,7 +263,7 @@ module system_top (
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.enable (enable),
.enable (enable_s),
.eth1_125mclk (),
.eth1_25mclk (),
.eth1_2m5clk (),
@ -336,7 +346,8 @@ module system_top (
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx));
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

4
projects/fmcomms2/vc707/system_constr.xdc
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@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN K30 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN W31 IOSTANDARD LVCMOS18} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN L29 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN K37 IOSTANDARD LVCMOS18} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K38 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN J30 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN H30 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

23
projects/fmcomms2/vc707/system_top.v
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@ -104,8 +104,9 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -183,8 +184,8 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -206,12 +207,21 @@ module system_top (
wire spi_mosi;
wire spi_miso;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// default logic
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
assign spi_csn_0 = spi_csn[0];
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
@ -301,7 +311,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
.uart_sout (uart_sout),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

4
projects/fmcomms2/zc702/system_constr.xdc
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@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

25
projects/fmcomms2/zc702/system_top.v
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@ -90,8 +90,9 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -152,8 +153,8 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -176,6 +177,17 @@ module system_top (
wire spi_udc_sclk;
wire spi_udc_data;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// internal logic
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(29)) i_iobuf (
@ -273,7 +285,10 @@ module system_top (
.spi1_csn_2_o(),
.spi1_sdo_i (spi_udc_data),
.spi1_sdo_o (spi_udc_data),
.spi1_sdi_i (1'b0));
.spi1_sdi_i (1'b0),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

28
projects/fmcomms2/zc706/system_top.v
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@ -89,6 +89,7 @@ module system_top (
tx_frame_out_n,
tx_data_out_p,
tx_data_out_n,
enable,
txnrx,
@ -156,6 +157,7 @@ module system_top (
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
output enable;
output txnrx;
@ -202,13 +204,24 @@ module system_top (
wire [31:0] dac_gpio_input;
wire [31:0] dac_gpio_output;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
.dio_t (gpio_t[46:32]),
.dio_i (gpio_o[46:32]),
.dio_o (gpio_i[46:32]),
.dio_p ({ gpio_resetb,
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
.dio_t (gpio_t[48:32]),
.dio_i (gpio_o[48:32]),
.dio_o (gpio_i[48:32]),
.dio_p ({ gpio_txnrx,
gpio_enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
gpio_ctl,
@ -236,7 +249,7 @@ module system_top (
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.enable (enable),
.enable (enable_s),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
@ -296,7 +309,8 @@ module system_top (
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx));
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule

4
projects/fmcomms2/zed/system_constr.xdc
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@ -50,8 +50,8 @@ set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N

26
projects/fmcomms2/zed/system_top.v
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@ -100,8 +100,9 @@ module system_top (
tx_data_out_p,
tx_data_out_n,
gpio_txnrx,
gpio_enable,
txnrx,
enable,
gpio_resetb,
gpio_sync,
gpio_en_agc,
@ -177,8 +178,9 @@ module system_top (
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
inout gpio_txnrx;
inout gpio_enable;
output txnrx;
output enable;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
@ -207,6 +209,17 @@ module system_top (
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire tdd_enable_s;
wire gpio_enable;
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
// internal logic
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
// instantiations
ad_iobuf #(.DATA_WIDTH(49)) i_iobuf_gpio (
@ -319,7 +332,10 @@ module system_top (
.tx_data_out_n (tx_data_out_n),
.tx_data_out_p (tx_data_out_p),
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p));
.tx_frame_out_p (tx_frame_out_p),
.enable (enable_s),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
endmodule