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axi_dmac: address_generator: Remove resets from data path 

There is no need to reset the data path in the address generator. The
values of the register on the data path are not used until they have been
explicitly initialized. Removing the reset simplifies the structure and
reduces the fan-out of the reset signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2015-09-11 10:46:55 +02:00 committed by Lars-Peter Clausen
parent 67600f9831
commit 6b7a46410c
1 changed files with 6 additions and 9 deletions
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15
library/axi_dmac/address_generator.v
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@ -109,6 +109,7 @@ end
always @(posedge clk) begin always @(posedge clk) begin
if (addr_valid == 1'b0) begin if (addr_valid == 1'b0) begin
last <= eot;
if (eot == 1'b1) if (eot == 1'b1)
length <= last_burst_len; length <= last_burst_len;
else else
@ -117,17 +118,16 @@ always @(posedge clk) begin
end end
always @(posedge clk) begin always @(posedge clk) begin
if (resetn == 1'b0) begin if (req_ready == 1'b1) begin
last <= 1'b0; address <= req_address;
end else if (addr_valid == 1'b0) begin last_burst_len <= req_last_burst_length;
last <= eot; end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin
address <= address + MAX_BEATS_PER_BURST;
end end
end end
always @(posedge clk) begin always @(posedge clk) begin
if (resetn == 1'b0) begin if (resetn == 1'b0) begin
address <= 'h00;
last_burst_len <= 'h00;
req_ready <= 1'b1; req_ready <= 1'b1;
addr_valid <= 1'b0; addr_valid <= 1'b0;
end else begin end else begin
@ -135,13 +135,10 @@ always @(posedge clk) begin
req_ready <= 1'b1; req_ready <= 1'b1;
end else if (req_ready) begin end else if (req_ready) begin
if (req_valid && enable) begin if (req_valid && enable) begin
address <= req_address;
req_ready <= 1'b0; req_ready <= 1'b0;
last_burst_len <= req_last_burst_length;
end end
end else begin end else begin
if (addr_valid && addr_ready) begin if (addr_valid && addr_ready) begin
address <= address + MAX_BEATS_PER_BURST;
addr_valid <= 1'b0; addr_valid <= 1'b0;
if (last) if (last)
req_ready <= 1'b1; req_ready <= 1'b1;