stap- need to be qsys

2015-06-29 13:26:32 -04:00 · 2015-06-29 13:26:32 -04:00 · 6bc24e25eb
parent d25e02d7ee
commit 6bc24e25eb
1 changed files with 1 additions and 0 deletions
--- a/projects/daq2/a10gx/system_project.tcl
+++ b/projects/daq2/a10gx/system_project.tcl
@ -8,6 +8,7 @@ source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl

 set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/ad_iobuf.v
 set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
+set_global_assignment -name QSYS_FILE system_stap.qsys

 # lane interface