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adrv9379: Initial commit

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Adrian Costina 2017-09-01 17:28:04 +03:00
parent 9a32240cc5
commit 6ce4494002
7 changed files with 895 additions and 0 deletions
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21
projects/adrv9379/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
.PHONY: all clean clean-all
all:
-make -C zc706 all
clean:
make -C zc706 clean
clean-all:
make -C zc706 clean-all
####################################################################################
####################################################################################

290
projects/adrv9379/common/adrv9379_bd.tcl Normal file
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# ad9379
create_bd_port -dir I dac_fifo_bypass
# dac peripherals
ad_ip_instance axi_clkgen axi_ad9379_tx_clkgen
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.ID 2
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.CLKIN_PERIOD 4
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.VCO_MUL 4
ad_ip_parameter axi_ad9379_tx_clkgen CONFIG.CLK0_DIV 4
ad_ip_instance axi_adxcvr axi_ad9379_tx_xcvr
ad_ip_parameter axi_ad9379_tx_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_ad9379_tx_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_ad9379_tx_xcvr CONFIG.TX_OR_RX_N 1
adi_axi_jesd204_tx_create axi_ad9379_tx_jesd 4
ad_ip_instance util_upack util_ad9379_tx_upack
ad_ip_parameter util_ad9379_tx_upack CONFIG.CHANNEL_DATA_WIDTH 32
ad_ip_parameter util_ad9379_tx_upack CONFIG.NUM_OF_CHANNELS 4
ad_ip_instance axi_dmac axi_ad9379_tx_dma
ad_ip_parameter axi_ad9379_tx_dma CONFIG.DMA_TYPE_SRC 0
ad_ip_parameter axi_ad9379_tx_dma CONFIG.DMA_TYPE_DEST 1
ad_ip_parameter axi_ad9379_tx_dma CONFIG.CYCLIC 1
ad_ip_parameter axi_ad9379_tx_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9379_tx_dma CONFIG.AXI_SLICE_DEST 1
ad_ip_parameter axi_ad9379_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_ad9379_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_ad9379_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_ad9379_tx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9379_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
# adc peripherals
ad_ip_instance axi_clkgen axi_ad9379_rx_clkgen
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.ID 2
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.CLKIN_PERIOD 4
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.VCO_MUL 4
ad_ip_parameter axi_ad9379_rx_clkgen CONFIG.CLK0_DIV 4
ad_ip_instance axi_adxcvr axi_ad9379_rx_xcvr
ad_ip_parameter axi_ad9379_rx_xcvr CONFIG.NUM_OF_LANES 2
ad_ip_parameter axi_ad9379_rx_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9379_rx_xcvr CONFIG.TX_OR_RX_N 0
adi_axi_jesd204_rx_create axi_ad9379_rx_jesd 2
ad_ip_instance util_cpack util_ad9379_rx_cpack
ad_ip_parameter util_ad9379_rx_cpack CONFIG.CHANNEL_DATA_WIDTH 16
ad_ip_parameter util_ad9379_rx_cpack CONFIG.NUM_OF_CHANNELS 4
ad_ip_instance axi_dmac axi_ad9379_rx_dma
ad_ip_parameter axi_ad9379_rx_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad9379_rx_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9379_rx_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9379_rx_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_ad9379_rx_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9379_rx_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9379_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_ad9379_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_ad9379_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_ad9379_rx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9379_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 64
# adc-os peripherals
ad_ip_instance axi_clkgen axi_ad9379_rx_os_clkgen
ad_ip_parameter axi_ad9379_rx_os_clkgen CONFIG.ID 2
ad_ip_parameter axi_ad9379_rx_os_clkgen CONFIG.CLKIN_PERIOD 4
ad_ip_parameter axi_ad9379_rx_os_clkgen CONFIG.VCO_DIV 1
ad_ip_parameter axi_ad9379_rx_os_clkgen CONFIG.VCO_MUL 4
ad_ip_parameter axi_ad9379_rx_os_clkgen CONFIG.CLK0_DIV 4
ad_ip_instance axi_adxcvr axi_ad9379_rx_os_xcvr
ad_ip_parameter axi_ad9379_rx_os_xcvr CONFIG.NUM_OF_LANES 2
ad_ip_parameter axi_ad9379_rx_os_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_ad9379_rx_os_xcvr CONFIG.TX_OR_RX_N 0
adi_axi_jesd204_rx_create axi_ad9379_rx_os_jesd 2
ad_ip_instance util_cpack util_ad9379_rx_os_cpack
ad_ip_parameter util_ad9379_rx_os_cpack CONFIG.CHANNEL_DATA_WIDTH 32
ad_ip_parameter util_ad9379_rx_os_cpack CONFIG.NUM_OF_CHANNELS 2
ad_ip_instance axi_dmac axi_ad9379_rx_os_dma
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad9379_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC 64
# common cores
ad_ip_instance axi_ad9379 axi_ad9379_core
ad_ip_instance util_adxcvr util_ad9379_xcvr
ad_ip_parameter util_ad9379_xcvr CONFIG.RX_NUM_OF_LANES 4
ad_ip_parameter util_ad9379_xcvr CONFIG.TX_NUM_OF_LANES 4
ad_ip_parameter util_ad9379_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_ad9379_xcvr CONFIG.CPLL_FBDIV 4
ad_ip_parameter util_ad9379_xcvr CONFIG.RX_CLK25_DIV 10
ad_ip_parameter util_ad9379_xcvr CONFIG.TX_CLK25_DIV 10
ad_ip_parameter util_ad9379_xcvr CONFIG.RX_PMA_CFG 0x001E7080
ad_ip_parameter util_ad9379_xcvr CONFIG.RX_CDR_CFG 0x0b000023ff10400020
ad_ip_parameter util_ad9379_xcvr CONFIG.QPLL_FBDIV 0x080
# xcvr interfaces
create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
create_bd_port -dir I rx_ref_clk_2
ad_xcvrpll tx_ref_clk_0 util_ad9379_xcvr/qpll_ref_clk_0
ad_xcvrpll rx_ref_clk_0 util_ad9379_xcvr/cpll_ref_clk_0
ad_xcvrpll rx_ref_clk_0 util_ad9379_xcvr/cpll_ref_clk_1
ad_xcvrpll rx_ref_clk_2 util_ad9379_xcvr/cpll_ref_clk_2
ad_xcvrpll rx_ref_clk_2 util_ad9379_xcvr/cpll_ref_clk_3
ad_xcvrpll axi_ad9379_tx_xcvr/up_pll_rst util_ad9379_xcvr/up_qpll_rst_0
ad_xcvrpll axi_ad9379_rx_xcvr/up_pll_rst util_ad9379_xcvr/up_cpll_rst_0
ad_xcvrpll axi_ad9379_rx_xcvr/up_pll_rst util_ad9379_xcvr/up_cpll_rst_1
ad_xcvrpll axi_ad9379_rx_os_xcvr/up_pll_rst util_ad9379_xcvr/up_cpll_rst_2
ad_xcvrpll axi_ad9379_rx_os_xcvr/up_pll_rst util_ad9379_xcvr/up_cpll_rst_3
ad_connect sys_cpu_resetn util_ad9379_xcvr/up_rstn
ad_connect sys_cpu_clk util_ad9379_xcvr/up_clk
ad_xcvrcon util_ad9379_xcvr axi_ad9379_tx_xcvr axi_ad9379_tx_jesd
ad_reconct util_ad9379_xcvr/tx_out_clk_0 axi_ad9379_tx_clkgen/clk
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_0
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_1
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_2
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_xcvr/tx_clk_3
ad_connect axi_ad9379_tx_clkgen/clk_0 axi_ad9379_tx_jesd/device_clk
ad_connect axi_ad9379_tx_clkgen/clk_0 axi_ad9379_tx_jesd_rstgen/slowest_sync_clk
ad_reconct util_ad9379_xcvr/tx_0 axi_ad9379_tx_jesd/tx_phy3
ad_reconct util_ad9379_xcvr/tx_1 axi_ad9379_tx_jesd/tx_phy0
ad_reconct util_ad9379_xcvr/tx_2 axi_ad9379_tx_jesd/tx_phy1
ad_reconct util_ad9379_xcvr/tx_3 axi_ad9379_tx_jesd/tx_phy2
ad_xcvrcon util_ad9379_xcvr axi_ad9379_rx_xcvr axi_ad9379_rx_jesd
ad_reconct util_ad9379_xcvr/rx_out_clk_0 axi_ad9379_rx_clkgen/clk
ad_connect axi_ad9379_rx_clkgen/clk_0 util_ad9379_xcvr/rx_clk_0
ad_connect axi_ad9379_rx_clkgen/clk_0 util_ad9379_xcvr/rx_clk_1
ad_connect axi_ad9379_rx_clkgen/clk_0 axi_ad9379_rx_jesd/device_clk
ad_connect axi_ad9379_rx_clkgen/clk_0 axi_ad9379_rx_jesd_rstgen/slowest_sync_clk
ad_xcvrcon util_ad9379_xcvr axi_ad9379_rx_os_xcvr axi_ad9379_rx_os_jesd
ad_reconct util_ad9379_xcvr/rx_out_clk_2 axi_ad9379_rx_os_clkgen/clk
ad_connect axi_ad9379_rx_os_clkgen/clk_0 util_ad9379_xcvr/rx_clk_2
ad_connect axi_ad9379_rx_os_clkgen/clk_0 util_ad9379_xcvr/rx_clk_3
ad_connect axi_ad9379_rx_os_clkgen/clk_0 axi_ad9379_rx_os_jesd/device_clk
ad_connect axi_ad9379_rx_os_clkgen/clk_0 axi_ad9379_rx_os_jesd_rstgen/slowest_sync_clk
# dma clock & reset
ad_ip_instance proc_sys_reset sys_dma_rstgen
ad_ip_parameter sys_dma_rstgen CONFIG.C_EXT_RST_WIDTH 1
ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset
ad_connect sys_dma_reset axi_ad9379_dacfifo/dma_rst
# connections (dac)
ad_connect axi_ad9379_tx_clkgen/clk_0 axi_ad9379_core/dac_clk
ad_connect axi_ad9379_tx_jesd/tx_data_tdata axi_ad9379_core/dac_tx_data
ad_connect axi_ad9379_tx_clkgen/clk_0 util_ad9379_tx_upack/dac_clk
ad_connect axi_ad9379_core/dac_valid_i0 util_ad9379_tx_upack/dac_valid_0
ad_connect axi_ad9379_core/dac_enable_i0 util_ad9379_tx_upack/dac_enable_0
ad_connect axi_ad9379_core/dac_data_i0 util_ad9379_tx_upack/dac_data_0
ad_connect axi_ad9379_core/dac_valid_q0 util_ad9379_tx_upack/dac_valid_1
ad_connect axi_ad9379_core/dac_enable_q0 util_ad9379_tx_upack/dac_enable_1
ad_connect axi_ad9379_core/dac_data_q0 util_ad9379_tx_upack/dac_data_1
ad_connect axi_ad9379_core/dac_valid_i1 util_ad9379_tx_upack/dac_valid_2
ad_connect axi_ad9379_core/dac_enable_i1 util_ad9379_tx_upack/dac_enable_2
ad_connect axi_ad9379_core/dac_data_i1 util_ad9379_tx_upack/dac_data_2
ad_connect axi_ad9379_core/dac_valid_q1 util_ad9379_tx_upack/dac_valid_3
ad_connect axi_ad9379_core/dac_enable_q1 util_ad9379_tx_upack/dac_enable_3
ad_connect axi_ad9379_core/dac_data_q1 util_ad9379_tx_upack/dac_data_3
ad_connect axi_ad9379_tx_clkgen/clk_0 axi_ad9379_dacfifo/dac_clk
ad_connect axi_ad9379_tx_jesd_rstgen/peripheral_reset axi_ad9379_dacfifo/dac_rst
ad_connect util_ad9379_tx_upack/dac_valid axi_ad9379_dacfifo/dac_valid
ad_connect util_ad9379_tx_upack/dac_data axi_ad9379_dacfifo/dac_data
ad_connect sys_dma_clk axi_ad9379_dacfifo/dma_clk
ad_connect sys_dma_clk axi_ad9379_tx_dma/m_axis_aclk
ad_connect axi_ad9379_dacfifo/dma_valid axi_ad9379_tx_dma/m_axis_valid
ad_connect axi_ad9379_dacfifo/dma_data axi_ad9379_tx_dma/m_axis_data
ad_connect axi_ad9379_dacfifo/dma_ready axi_ad9379_tx_dma/m_axis_ready
ad_connect axi_ad9379_dacfifo/dma_xfer_req axi_ad9379_tx_dma/m_axis_xfer_req
ad_connect axi_ad9379_dacfifo/dma_xfer_last axi_ad9379_tx_dma/m_axis_last
ad_connect axi_ad9379_dacfifo/dac_dunf axi_ad9379_core/dac_dunf
ad_connect axi_ad9379_dacfifo/bypass dac_fifo_bypass
ad_connect sys_dma_resetn axi_ad9379_tx_dma/m_src_axi_aresetn
# connections (adc)
ad_connect axi_ad9379_rx_clkgen/clk_0 axi_ad9379_core/adc_clk
ad_connect axi_ad9379_rx_jesd/rx_sof axi_ad9379_core/adc_rx_sof
ad_connect axi_ad9379_rx_jesd/rx_data_tdata axi_ad9379_core/adc_rx_data
ad_connect axi_ad9379_rx_clkgen/clk_0 util_ad9379_rx_cpack/adc_clk
ad_connect axi_ad9379_rx_jesd_rstgen/peripheral_reset util_ad9379_rx_cpack/adc_rst
ad_connect axi_ad9379_core/adc_enable_i0 util_ad9379_rx_cpack/adc_enable_0
ad_connect axi_ad9379_core/adc_valid_i0 util_ad9379_rx_cpack/adc_valid_0
ad_connect axi_ad9379_core/adc_data_i0 util_ad9379_rx_cpack/adc_data_0
ad_connect axi_ad9379_core/adc_enable_q0 util_ad9379_rx_cpack/adc_enable_1
ad_connect axi_ad9379_core/adc_valid_q0 util_ad9379_rx_cpack/adc_valid_1
ad_connect axi_ad9379_core/adc_data_q0 util_ad9379_rx_cpack/adc_data_1
ad_connect axi_ad9379_core/adc_enable_i1 util_ad9379_rx_cpack/adc_enable_2
ad_connect axi_ad9379_core/adc_valid_i1 util_ad9379_rx_cpack/adc_valid_2
ad_connect axi_ad9379_core/adc_data_i1 util_ad9379_rx_cpack/adc_data_2
ad_connect axi_ad9379_core/adc_enable_q1 util_ad9379_rx_cpack/adc_enable_3
ad_connect axi_ad9379_core/adc_valid_q1 util_ad9379_rx_cpack/adc_valid_3
ad_connect axi_ad9379_core/adc_data_q1 util_ad9379_rx_cpack/adc_data_3
ad_connect axi_ad9379_rx_clkgen/clk_0 axi_ad9379_rx_dma/fifo_wr_clk
ad_connect util_ad9379_rx_cpack/adc_valid axi_ad9379_rx_dma/fifo_wr_en
ad_connect util_ad9379_rx_cpack/adc_sync axi_ad9379_rx_dma/fifo_wr_sync
ad_connect util_ad9379_rx_cpack/adc_data axi_ad9379_rx_dma/fifo_wr_din
ad_connect axi_ad9379_rx_dma/fifo_wr_overflow axi_ad9379_core/adc_dovf
ad_connect sys_dma_resetn axi_ad9379_rx_dma/m_dest_axi_aresetn
# connections (adc-os)
ad_connect axi_ad9379_rx_os_clkgen/clk_0 axi_ad9379_core/adc_os_clk
ad_connect axi_ad9379_rx_os_jesd/rx_sof axi_ad9379_core/adc_rx_os_sof
ad_connect axi_ad9379_rx_os_jesd/rx_data_tdata axi_ad9379_core/adc_rx_os_data
ad_connect axi_ad9379_rx_os_clkgen/clk_0 util_ad9379_rx_os_cpack/adc_clk
ad_connect axi_ad9379_rx_os_jesd_rstgen/peripheral_reset util_ad9379_rx_os_cpack/adc_rst
ad_connect axi_ad9379_core/adc_os_enable_i0 util_ad9379_rx_os_cpack/adc_enable_0
ad_connect axi_ad9379_core/adc_os_valid_i0 util_ad9379_rx_os_cpack/adc_valid_0
ad_connect axi_ad9379_core/adc_os_data_i0 util_ad9379_rx_os_cpack/adc_data_0
ad_connect axi_ad9379_core/adc_os_enable_q0 util_ad9379_rx_os_cpack/adc_enable_1
ad_connect axi_ad9379_core/adc_os_valid_q0 util_ad9379_rx_os_cpack/adc_valid_1
ad_connect axi_ad9379_core/adc_os_data_q0 util_ad9379_rx_os_cpack/adc_data_1
ad_connect axi_ad9379_rx_os_clkgen/clk_0 axi_ad9379_rx_os_dma/fifo_wr_clk
ad_connect util_ad9379_rx_os_cpack/adc_valid axi_ad9379_rx_os_dma/fifo_wr_en
ad_connect util_ad9379_rx_os_cpack/adc_sync axi_ad9379_rx_os_dma/fifo_wr_sync
ad_connect util_ad9379_rx_os_cpack/adc_data axi_ad9379_rx_os_dma/fifo_wr_din
ad_connect axi_ad9379_rx_os_dma/fifo_wr_overflow axi_ad9379_core/adc_os_dovf
ad_connect sys_dma_resetn axi_ad9379_rx_os_dma/m_dest_axi_aresetn
# interconnect (cpu)
ad_cpu_interconnect 0x44A00000 axi_ad9379_core
ad_cpu_interconnect 0x44A80000 axi_ad9379_tx_xcvr
ad_cpu_interconnect 0x43C00000 axi_ad9379_tx_clkgen
ad_cpu_interconnect 0x44A90000 axi_ad9379_tx_jesd
ad_cpu_interconnect 0x7c420000 axi_ad9379_tx_dma
ad_cpu_interconnect 0x44A60000 axi_ad9379_rx_xcvr
ad_cpu_interconnect 0x43C10000 axi_ad9379_rx_clkgen
ad_cpu_interconnect 0x44AA0000 axi_ad9379_rx_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9379_rx_dma
ad_cpu_interconnect 0x44A50000 axi_ad9379_rx_os_xcvr
ad_cpu_interconnect 0x43C20000 axi_ad9379_rx_os_clkgen
ad_cpu_interconnect 0x44AB0000 axi_ad9379_rx_os_jesd
ad_cpu_interconnect 0x7c440000 axi_ad9379_rx_os_dma
# gt uses hp3, and 100MHz clock for both DRP and AXI4
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9379_rx_xcvr/m_axi
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9379_rx_os_xcvr/m_axi
# interconnect (mem/dac)
ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_dma_clk axi_ad9379_tx_dma/m_src_axi
ad_mem_hp2_interconnect sys_dma_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_dma_clk axi_ad9379_rx_dma/m_dest_axi
ad_mem_hp2_interconnect sys_dma_clk axi_ad9379_rx_os_dma/m_dest_axi
# interrupts
ad_cpu_interrupt ps-8 mb-8 axi_ad9379_rx_os_jesd/irq
ad_cpu_interrupt ps-9 mb-7 axi_ad9379_tx_jesd/irq
ad_cpu_interrupt ps-10 mb-15 axi_ad9379_rx_jesd/irq
ad_cpu_interrupt ps-11 mb-14 axi_ad9379_rx_os_dma/irq
ad_cpu_interrupt ps-12 mb-13- axi_ad9379_tx_dma/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9379_rx_dma/irq

105
projects/adrv9379/zc706/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/adrv9379_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../common/zc706/zc706_plddr3_dacfifo_bd.tcl
M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/axi_ad9379/axi_ad9379.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx.xpr
M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib adrv9379_zc706.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad9379 clean
make -C ../../../library/xilinx/axi_adxcvr clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/xilinx/axi_dacfifo clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/jesd204/axi_jesd204_rx clean
make -C ../../../library/jesd204/axi_jesd204_tx clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/jesd204/jesd204_rx clean
make -C ../../../library/jesd204/jesd204_tx clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_upack clean
adrv9379_zc706.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> adrv9379_zc706_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad9379
make -C ../../../library/xilinx/axi_adxcvr
make -C ../../../library/axi_clkgen
make -C ../../../library/xilinx/axi_dacfifo
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/jesd204/axi_jesd204_rx
make -C ../../../library/jesd204/axi_jesd204_tx
make -C ../../../library/axi_spdif_tx
make -C ../../../library/jesd204/jesd204_rx
make -C ../../../library/jesd204/jesd204_tx
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_bsplit
make -C ../../../library/util_cpack
make -C ../../../library/util_upack
####################################################################################
####################################################################################

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set dac_fifo_name axi_ad9379_dacfifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 150
source ../common/adrv9379_bd.tcl
ad_connect sys_dma_clk sys_ps7/FCLK_CLK2
ad_connect sys_ps7/FCLK_RESET2_N sys_dma_rstgen/ext_reset_in

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# ad9379
set_property -dict {PACKAGE_PIN AD10} [get_ports ref_clk0_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P (NC)
set_property -dict {PACKAGE_PIN AD9 } [get_ports ref_clk0_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N (NC)
set_property -dict {PACKAGE_PIN AA8 } [get_ports ref_clk1_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P
set_property -dict {PACKAGE_PIN AA7 } [get_ports ref_clk1_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[0]] ; ## A02 FMC_HPC_DP1_M2C_P
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[0]] ; ## A03 FMC_HPC_DP1_M2C_N
set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[1]] ; ## A06 FMC_HPC_DP2_M2C_P
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[1]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[2]] ; ## C06 FMC_HPC_DP0_M2C_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[2]] ; ## C07 FMC_HPC_DP0_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[0]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[0])
set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[0]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[0])
set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[3]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[1])
set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[3]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[1])
set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[2]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[2])
set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[2]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[2])
set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[3])
set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[3])
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_p] ; ## G27 FMC_HPC_LA25_P (Sniffer)
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVDS_25} [get_ports rx_os_sync_n] ; ## G28 FMC_HPC_LA25_N (Sniffer)
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_p] ; ## G06 FMC_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_n] ; ## G07 FMC_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_1_p] ; ## H28 FMC_HPC_LA24_P
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_1_n] ; ## H29 FMC_HPC_LA24_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_out_p] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sysref_out_n] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9528] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9379] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports ad9528_reset_b] ; ## D26 FMC_HPC_LA26_P
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports ad9528_sysref_req] ; ## D27 FMC_HPC_LA26_N
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports ad9379_tx1_enable] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports ad9379_tx2_enable] ; ## C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports ad9379_rx1_enable] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports ad9379_rx2_enable] ; ## C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports ad9379_test] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports ad9379_reset_b] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports ad9379_gpint] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_00] ; ## H19 FMC_HPC_LA15_P
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_01] ; ## H20 FMC_HPC_LA15_N
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_02] ; ## G18 FMC_HPC_LA16_P
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_03] ; ## G19 FMC_HPC_LA16_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_04] ; ## H25 FMC_HPC_LA21_P
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_05] ; ## H26 FMC_HPC_LA21_N
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_06] ; ## C22 FMC_HPC_LA18_CC_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_07] ; ## C23 FMC_HPC_LA18_CC_N
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_08] ; ## G25 FMC_HPC_LA22_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_09] ; ## H22 FMC_HPC_LA19_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_10] ; ## H23 FMC_HPC_LA19_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_11] ; ## G21 FMC_HPC_LA20_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_12] ; ## G22 FMC_HPC_LA20_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_13] ; ## G31 FMC_HPC_LA29_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_14] ; ## G30 FMC_HPC_LA29_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_15] ; ## G24 FMC_HPC_LA22_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_16] ; ## G03 FMC_HPC_CLK1_M2C_N (LVDS Pairs?)
set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_17] ; ## G02 FMC_HPC_CLK1_M2C_P (LVDS Pairs?)
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports ad9379_gpio_18] ; ## D12 FMC_HPC_LA05_N
# clocks
create_clock -name tx_ref_clk -period 4.00 [get_ports ref_clk0_p]
create_clock -name rx_ref_clk -period 4.00 [get_ports ref_clk1_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_os_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9379_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9379_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9379_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_xilinx adrv9379_zc706
adi_project_files adrv9379_zc706 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run adrv9379_zc706

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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
inout iic_scl,
inout iic_sda,
input ref_clk0_p,
input ref_clk0_n,
input ref_clk1_p,
input ref_clk1_n,
input [ 3:0] rx_data_p,
input [ 3:0] rx_data_n,
output [ 3:0] tx_data_p,
output [ 3:0] tx_data_n,
output rx_sync_p,
output rx_sync_n,
output rx_os_sync_p,
output rx_os_sync_n,
input tx_sync_p,
input tx_sync_n,
input tx_sync_1_p,
input tx_sync_1_n,
input sysref_p,
input sysref_n,
output sysref_out_p,
output sysref_out_n,
output spi_csn_ad9528,
output spi_csn_ad9379,
output spi_clk,
output spi_mosi,
input spi_miso,
inout ad9528_reset_b,
inout ad9528_sysref_req,
inout ad9379_tx1_enable,
inout ad9379_tx2_enable,
inout ad9379_rx1_enable,
inout ad9379_rx2_enable,
inout ad9379_test,
inout ad9379_reset_b,
inout ad9379_gpint,
inout ad9379_gpio_00,
inout ad9379_gpio_01,
inout ad9379_gpio_02,
inout ad9379_gpio_03,
inout ad9379_gpio_04,
inout ad9379_gpio_05,
inout ad9379_gpio_06,
inout ad9379_gpio_07,
inout ad9379_gpio_15,
inout ad9379_gpio_08,
inout ad9379_gpio_09,
inout ad9379_gpio_10,
inout ad9379_gpio_11,
inout ad9379_gpio_12,
inout ad9379_gpio_14,
inout ad9379_gpio_13,
inout ad9379_gpio_17,
inout ad9379_gpio_16,
inout ad9379_gpio_18,
input sys_rst,
input sys_clk_p,
input sys_clk_n,
output [13:0] ddr3_addr,
output [ 2:0] ddr3_ba,
output ddr3_cas_n,
output [ 0:0] ddr3_ck_n,
output [ 0:0] ddr3_ck_p,
output [ 0:0] ddr3_cke,
output [ 0:0] ddr3_cs_n,
output [ 7:0] ddr3_dm,
inout [63:0] ddr3_dq,
inout [ 7:0] ddr3_dqs_n,
inout [ 7:0] ddr3_dqs_p,
output [ 0:0] ddr3_odt,
output ddr3_ras_n,
output ddr3_reset_n,
output ddr3_we_n);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire ref_clk0;
wire ref_clk1;
wire rx_sync;
wire rx_os_sync;
wire tx_sync;
wire tx_sync_1;
wire sysref;
// wire sysref_out;
assign sysref_out = 0;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (ref_clk0_p),
.IB (ref_clk0_n),
.O (ref_clk0),
.ODIV2 ());
IBUFDS_GTE2 i_ibufds_ref_clk1 (
.CEB (1'd0),
.I (ref_clk1_p),
.IB (ref_clk1_n),
.O (ref_clk1),
.ODIV2 ());
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
OBUFDS i_obufds_rx_os_sync (
.I (rx_os_sync),
.O (rx_os_sync_p),
.OB (rx_os_sync_n));
OBUFDS i_obufds_sysref_out (
.I (sysref_out),
.O (sysref_out_p),
.OB (sysref_out_n));
IBUFDS i_ibufds_tx_sync (
.I (tx_sync_p),
.IB (tx_sync_n),
.O (tx_sync));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_1_p),
.IB (tx_sync_1_n),
.O (tx_sync_1));
IBUFDS i_ibufds_sysref (
.I (sysref_p),
.IB (sysref_n),
.O (sysref));
ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
.dio_t ({gpio_t[59:32]}),
.dio_i ({gpio_o[59:32]}),
.dio_o ({gpio_i[59:32]}),
.dio_p ({ ad9528_reset_b, // 59
ad9528_sysref_req, // 58
ad9379_tx1_enable, // 57
ad9379_tx2_enable, // 56
ad9379_rx1_enable, // 55
ad9379_rx2_enable, // 54
ad9379_test, // 53
ad9379_reset_b, // 52
ad9379_gpint, // 51
ad9379_gpio_00, // 50
ad9379_gpio_01, // 49
ad9379_gpio_02, // 48
ad9379_gpio_03, // 47
ad9379_gpio_04, // 46
ad9379_gpio_05, // 45
ad9379_gpio_06, // 44
ad9379_gpio_07, // 43
ad9379_gpio_15, // 42
ad9379_gpio_08, // 41
ad9379_gpio_09, // 40
ad9379_gpio_10, // 39
ad9379_gpio_11, // 38
ad9379_gpio_12, // 37
ad9379_gpio_14, // 36
ad9379_gpio_13, // 35
ad9379_gpio_17, // 34
ad9379_gpio_16, // 33
ad9379_gpio_18})); // 32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.dac_fifo_bypass (gpio_o[60]),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.rx_data_0_n (rx_data_n[0]),
.rx_data_0_p (rx_data_p[0]),
.rx_data_1_n (rx_data_n[1]),
.rx_data_1_p (rx_data_p[1]),
.rx_data_2_n (rx_data_n[2]),
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (ref_clk1),
.rx_ref_clk_2 (ref_clk1),
.rx_sync_0 (rx_sync),
.rx_sync_2 (rx_os_sync),
.rx_sysref_0 (sysref),
.rx_sysref_2 (sysref),
.spdif (spdif),
.spi0_clk_i (spi_clk),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn_ad9379),
.spi0_csn_1_o (spi_csn_ad9528),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (spi_mosi),
.spi0_sdo_o (spi_mosi),
.spi1_clk_i (1'd0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'd0),
.spi1_sdo_i (1'd0),
.spi1_sdo_o (),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.sys_rst(sys_rst),
.tx_data_0_n (tx_data_n[0]),
.tx_data_0_p (tx_data_p[0]),
.tx_data_1_n (tx_data_n[1]),
.tx_data_1_p (tx_data_p[1]),
.tx_data_2_n (tx_data_n[2]),
.tx_data_2_p (tx_data_p[2]),
.tx_data_3_n (tx_data_n[3]),
.tx_data_3_p (tx_data_p[3]),
.tx_ref_clk_0 (ref_clk1),
.tx_sync_0 (tx_sync),
.tx_sysref_0 (sysref));
endmodule
// ***************************************************************************
// ***************************************************************************