common: Allow for the memory to be also symetrical

2015-11-04 13:28:02 +02:00 · 2015-11-04 13:28:02 +02:00 · 6cfc13a9dd
parent ad1cef1441
commit 6cfc13a9dd
1 changed files with 8 additions and 0 deletions
--- a/library/common/ad_mem_asym.v
+++ b/library/common/ad_mem_asym.v
@ -81,6 +81,14 @@ module ad_mem_asym (
  // write interface

  generate
+  if (MEM_RATIO == 1) begin
+  always @(posedge clka) begin
+    if (wea == 1'b1) begin
+      m_ram[addra] <= dina;
+    end
+  end
+  end
+
  if (MEM_RATIO == 2) begin
  always @(posedge clka) begin
    if (wea == 1'b1) begin