avl_dacfifo: dma_ready was muxed incorrectly

2017-05-15 12:35:35 +03:00 · 2017-05-15 12:35:35 +03:00 · 6d52034abb
parent da68705fee
commit 6d52034abb
1 changed files with 1 additions and 1 deletions
--- a/library/altera/avl_dacfifo/avl_dacfifo.v
+++ b/library/altera/avl_dacfifo/avl_dacfifo.v
@ -229,7 +229,7 @@ module avl_dacfifo #(
    // mux for the dma_ready

    always @(posedge dma_clk) begin
-      dma_ready <= (dma_bypass) ? dma_ready_wr_s : dma_ready_bypass_s;
+      dma_ready <= (dma_bypass) ? dma_ready_bypass_s : dma_ready_wr_s;
    end

    // mux for dac data