From 6d5b5b50a561ad84c0b2b145ad3756ffd7045300 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 30 Aug 2017 18:17:41 +0300
Subject: [PATCH] axi_logic_analyzer: Compensate the 4 word latency of
 util_var_fifo

---
 .../axi_logic_analyzer/axi_logic_analyzer.v   | 28 ++++++++++---------
 .../axi_logic_analyzer_trigger.v              |  8 +++++-
 2 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/library/axi_logic_analyzer/axi_logic_analyzer.v b/library/axi_logic_analyzer/axi_logic_analyzer.v
index aec2487bb..c57fe3b1e 100644
--- a/library/axi_logic_analyzer/axi_logic_analyzer.v
+++ b/library/axi_logic_analyzer/axi_logic_analyzer.v
@@ -46,7 +46,7 @@ module axi_logic_analyzer (
   input       [ 1:0]    trigger_i,
 
   output reg            adc_valid,
-  output reg  [15:0]    adc_data,
+  output      [15:0]    adc_data,
 
   input       [15:0]    dac_data,
   input                 dac_valid,
@@ -89,8 +89,6 @@ module axi_logic_analyzer (
   reg     [31:0]    upsampler_counter_pg = 'd0;
 
   reg               sample_valid_la = 'd0;
-  reg               adc_valid_d1 = 'd0;
-  reg               adc_valid_d2 = 'd0;
 
   reg     [15:0]    io_selection; // 1 - input, 0 - output
 
@@ -108,6 +106,8 @@ module axi_logic_analyzer (
 
   reg               streaming_on;
 
+  reg     [15:0]    adc_data_m2 = 'd0;
+
   // internal signals
 
   wire              up_clk;
@@ -155,6 +155,8 @@ module axi_logic_analyzer (
   assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on;
   assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
 
+  assign adc_data = adc_data_m2;
+
  always @(posedge clk_out) begin
     if (trigger_delay == 0) begin
       if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin
@@ -218,22 +220,22 @@ module axi_logic_analyzer (
   // synchronization
 
   always @(posedge clk_out) begin
-    data_m1 <= data_i;
-    trigger_m1 <= trigger_i;
-    trigger_m2 <= trigger_m1;
+    if (sample_valid_la == 1'b1) begin
+      data_m1 <= data_i;
+      trigger_m1 <= trigger_i;
+      trigger_m2 <= trigger_m1;
+    end
   end
 
   // transfer data at clock frequency
   // if capture is enabled
 
   always @(posedge clk_out) begin
-    adc_valid_d1 <= adc_valid_d2;
-    adc_valid <= adc_valid_d1;
     if (sample_valid_la == 1'b1) begin
-      adc_data  <= data_m1;
-      adc_valid_d2 <= 1'b1;
+      adc_data_m2  <= data_m1;
+      adc_valid <= 1'b1;
     end else begin
-      adc_valid_d2 <= 1'b0;
+      adc_valid <= 1'b0;
     end
   end
 
@@ -293,7 +295,7 @@ module axi_logic_analyzer (
     .clk (clk_out),
     .reset (reset),
 
-    .data (adc_data),
+    .data (adc_data_m2),
     .data_valid(sample_valid_la),
     .trigger (trigger_m2),
 
@@ -325,7 +327,7 @@ module axi_logic_analyzer (
     .clock_select (clock_select),
     .overwrite_enable (overwrite_enable),
     .overwrite_data (overwrite_data),
-    .input_data (adc_data),
+    .input_data (adc_data_m2),
     .od_pp_n (od_pp_n),
 
     .triggered (up_triggered),
diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
index cb7df5d7f..e53aa5793 100644
--- a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
+++ b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
@@ -63,9 +63,15 @@ module axi_logic_analyzer_trigger (
   reg     [ 31:0]   delay_count = 'd0;
 
   reg              trigger_active;
+  reg              trigger_active_d1;
+  reg              trigger_active_d2;
 
   always @(posedge clk) begin
-    trigger_out <= trigger_active;
+    if (data_valid == 1'b1) begin
+      trigger_active_d1 <= trigger_active;
+      trigger_active_d2 <= trigger_active_d1;
+      trigger_out <= trigger_active_d2;
+    end
   end
 
   // trigger logic: