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axi_logic_analyzer: Compensate the 4 word latency of util_var_fifo

main
Adrian Costina 2017-08-30 18:17:41 +03:00
parent f6288dc0a3
commit 6d5b5b50a5
2 changed files with 22 additions and 14 deletions
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22
library/axi_logic_analyzer/axi_logic_analyzer.v
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@ -46,7 +46,7 @@ module axi_logic_analyzer (
input [ 1:0] trigger_i, input [ 1:0] trigger_i,
output reg adc_valid, output reg adc_valid,
output reg [15:0] adc_data, output [15:0] adc_data,
input [15:0] dac_data, input [15:0] dac_data,
input dac_valid, input dac_valid,
@ -89,8 +89,6 @@ module axi_logic_analyzer (
reg [31:0] upsampler_counter_pg = 'd0; reg [31:0] upsampler_counter_pg = 'd0;
reg sample_valid_la = 'd0; reg sample_valid_la = 'd0;
reg adc_valid_d1 = 'd0;
reg adc_valid_d2 = 'd0;
reg [15:0] io_selection; // 1 - input, 0 - output reg [15:0] io_selection; // 1 - input, 0 - output
@ -108,6 +106,8 @@ module axi_logic_analyzer (
reg streaming_on; reg streaming_on;
reg [15:0] adc_data_m2 = 'd0;
// internal signals // internal signals
wire up_clk; wire up_clk;
@ -155,6 +155,8 @@ module axi_logic_analyzer (
assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on; assign trigger_out = trigger_delay == 32'h0 ? trigger_out_s | streaming_on : trigger_out_delayed | streaming_on;
assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0; assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0;
assign adc_data = adc_data_m2;
always @(posedge clk_out) begin always @(posedge clk_out) begin
if (trigger_delay == 0) begin if (trigger_delay == 0) begin
if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_s == 1'b1) begin
@ -218,22 +220,22 @@ module axi_logic_analyzer (
// synchronization // synchronization
always @(posedge clk_out) begin always @(posedge clk_out) begin
if (sample_valid_la == 1'b1) begin
data_m1 <= data_i; data_m1 <= data_i;
trigger_m1 <= trigger_i; trigger_m1 <= trigger_i;
trigger_m2 <= trigger_m1; trigger_m2 <= trigger_m1;
end end
end
// transfer data at clock frequency // transfer data at clock frequency
// if capture is enabled // if capture is enabled
always @(posedge clk_out) begin always @(posedge clk_out) begin
adc_valid_d1 <= adc_valid_d2;
adc_valid <= adc_valid_d1;
if (sample_valid_la == 1'b1) begin if (sample_valid_la == 1'b1) begin
adc_data <= data_m1; adc_data_m2 <= data_m1;
adc_valid_d2 <= 1'b1; adc_valid <= 1'b1;
end else begin end else begin
adc_valid_d2 <= 1'b0; adc_valid <= 1'b0;
end end
end end
@ -293,7 +295,7 @@ module axi_logic_analyzer (
.clk (clk_out), .clk (clk_out),
.reset (reset), .reset (reset),
.data (adc_data), .data (adc_data_m2),
.data_valid(sample_valid_la), .data_valid(sample_valid_la),
.trigger (trigger_m2), .trigger (trigger_m2),
@ -325,7 +327,7 @@ module axi_logic_analyzer (
.clock_select (clock_select), .clock_select (clock_select),
.overwrite_enable (overwrite_enable), .overwrite_enable (overwrite_enable),
.overwrite_data (overwrite_data), .overwrite_data (overwrite_data),
.input_data (adc_data), .input_data (adc_data_m2),
.od_pp_n (od_pp_n), .od_pp_n (od_pp_n),
.triggered (up_triggered), .triggered (up_triggered),

8
library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
View File

@ -63,9 +63,15 @@ module axi_logic_analyzer_trigger (
reg [ 31:0] delay_count = 'd0; reg [ 31:0] delay_count = 'd0;
reg trigger_active; reg trigger_active;
reg trigger_active_d1;
reg trigger_active_d2;
always @(posedge clk) begin always @(posedge clk) begin
trigger_out <= trigger_active; if (data_valid == 1'b1) begin
trigger_active_d1 <= trigger_active;
trigger_active_d2 <= trigger_active_d1;
trigger_out <= trigger_active_d2;
end
end end
// trigger logic: // trigger logic: