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altera/ad_mem_asym: Fix grounded bus for marco instance 

The "'b0" constant will be translate as a 32 bit width vector by
ModelSim, and will throw a buswidth mismatch error. Tie the data_b
bus to zero, using its width parameter.
main
Istvan Csomortani 2017-05-10 12:41:02 +03:00
parent d883aabcc1
commit 6dbbe2f1ca
1 changed files with 2 additions and 2 deletions
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4
library/altera/common/ad_mem_asym.v
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@ -29,7 +29,7 @@
module ad_mem_asym #( module ad_mem_asym #(
// parameters // parameters
parameter A_ADDRESS_WIDTH = 8, parameter A_ADDRESS_WIDTH = 8,
parameter A_DATA_WIDTH = 256, parameter A_DATA_WIDTH = 256,
parameter B_ADDRESS_WIDTH = 10, parameter B_ADDRESS_WIDTH = 10,
@ -83,7 +83,7 @@ module ad_mem_asym #(
.clock1 (clkb), .clock1 (clkb),
.address_b (addrb), .address_b (addrb),
.wren_b (1'b0), .wren_b (1'b0),
.data_b ('d0), .data_b ({B_DATA_WIDTH{1'd0}}),
.rden_b (1'b1), .rden_b (1'b1),
.q_b (doutb), .q_b (doutb),
.address2_a (1'b1), .address2_a (1'b1),