altera/ad_mem_asym: Fix grounded bus for marco instance

The "'b0" constant will be translate as a 32 bit width vector by ModelSim, and will throw a buswidth mismatch error. Tie the data_b bus to zero, using its width parameter.
2017-05-10 12:41:02 +03:00 · 2017-05-10 12:41:02 +03:00 · 6dbbe2f1ca
parent d883aabcc1
commit 6dbbe2f1ca
1 changed files with 2 additions and 2 deletions
--- a/library/altera/common/ad_mem_asym.v
+++ b/library/altera/common/ad_mem_asym.v
@ -83,7 +83,7 @@ module ad_mem_asym #(
    .clock1 (clkb),
    .address_b (addrb),
    .wren_b (1'b0),
-    .data_b ('d0),
+    .data_b ({B_DATA_WIDTH{1'd0}}),
    .rden_b (1'b1),
    .q_b (doutb),
    .address2_a (1'b1),