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axi_jesd_xcvr: individual reset control

main
Rejeesh Kutty 2015-07-13 10:04:34 -04:00
parent 8d6c39d307
commit 6e3817d419
3 changed files with 216 additions and 109 deletions
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150
library/axi_jesd_xcvr/axi_jesd_xcvr.v
View File

@ -39,29 +39,24 @@
module axi_jesd_xcvr ( module axi_jesd_xcvr (
// common reset
rst,
// receive interface // receive interface
rx_ref_clk,
rx_d,
rx_clk, rx_clk,
rx_rst,
rx_ext_sysref, rx_ext_sysref,
rx_sysref,
rx_ip_sync,
rx_sync, rx_sync,
rx_status, rx_sof,
rx_data,
// transmit interface // transmit interface
tx_ref_clk,
tx_d,
tx_clk, tx_clk,
tx_rst,
tx_ext_sysref, tx_ext_sysref,
tx_sysref,
tx_sync, tx_sync,
tx_ip_sync, tx_data,
tx_status,
// axi-lite (slave) // axi-lite (slave)
@ -85,36 +80,39 @@ module axi_jesd_xcvr (
s_axi_rvalid, s_axi_rvalid,
s_axi_rdata, s_axi_rdata,
s_axi_rresp, s_axi_rresp,
s_axi_rready); s_axi_rready,
// signal tap interface
stp_clk,
stp_data,
stp_trigger);
parameter PCORE_ID = 0; parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0; parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_NUM_OF_TX_LANES = 4; parameter PCORE_NUM_OF_TX_LANES = 4;
parameter PCORE_NUM_OF_RX_LANES = 4; parameter PCORE_NUM_OF_RX_LANES = 4;
parameter PCORE_ST_DATA_WIDTH = 32;
// common reset parameter PCORE_ST_TRIGGER_WIDTH = 4;
output rst;
// receive interface // receive interface
input rx_clk; input rx_ref_clk;
output rx_rst; input [(PCORE_NUM_OF_RX_LANES-1):0] rx_d;
output rx_clk;
input rx_ext_sysref; input rx_ext_sysref;
output rx_sysref;
input rx_ip_sync;
output rx_sync; output rx_sync;
input [(PCORE_NUM_OF_RX_LANES-1):0] rx_status; output [((PCORE_NUM_OF_RX_LANES* 1)-1):0] rx_sof;
output [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_data;
// transmit interface // transmit interface
input tx_clk; input tx_ref_clk;
output tx_rst; output [(PCORE_NUM_OF_TX_LANES-1):0] tx_d;
output tx_clk;
input tx_ext_sysref; input tx_ext_sysref;
output tx_sysref;
input tx_sync; input tx_sync;
output tx_ip_sync; input [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_data;
input [(PCORE_NUM_OF_RX_LANES-1):0] tx_status;
// axi interface // axi interface
@ -140,12 +138,30 @@ module axi_jesd_xcvr (
output [ 1:0] s_axi_rresp; output [ 1:0] s_axi_rresp;
input s_axi_rready; input s_axi_rready;
// signal tap interface
output stp_clk;
output [(PCORE_ST_DATA_WIDTH-1):0] stp_data;
output [(PCORE_ST_TRIGGER_WIDTH-1):0] stp_trigger;
// internal signals // internal signals
wire up_rstn; wire up_rstn;
wire up_clk; wire up_clk;
wire [ 7:0] status_s; wire [ 7:0] status_s;
wire rst;
wire rx_rstn;
wire rx_sysref_s;
wire rx_ip_sync_s;
wire [ 3:0] rx_ip_sof_s;
wire [((PCORE_NUM_OF_RX_LANES*32)-1):0] rx_ip_data_s;
wire [(PCORE_NUM_OF_RX_LANES-1):0] rx_ready_s;
wire [ 7:0] rx_status_s; wire [ 7:0] rx_status_s;
wire tx_rstn;
wire tx_sysref_s;
wire tx_ip_sync_s;
wire [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_ip_data_s;
wire [(PCORE_NUM_OF_TX_LANES-1):0] tx_ready_s;
wire [ 7:0] tx_status_s; wire [ 7:0] tx_status_s;
wire up_wreq_s; wire up_wreq_s;
wire [ 13:0] up_waddr_s; wire [ 13:0] up_waddr_s;
@ -165,38 +181,94 @@ module axi_jesd_xcvr (
generate generate
if (PCORE_NUM_OF_TX_LANES < 8) begin if (PCORE_NUM_OF_TX_LANES < 8) begin
assign tx_status_s[7:PCORE_NUM_OF_TX_LANES] = status_s[7:PCORE_NUM_OF_TX_LANES]; assign tx_status_s[7:PCORE_NUM_OF_TX_LANES] = status_s[7:PCORE_NUM_OF_TX_LANES];
assign tx_status_s[(PCORE_NUM_OF_TX_LANES-1):0] = tx_status; assign tx_status_s[(PCORE_NUM_OF_TX_LANES-1):0] = tx_ready_s;
end else begin end else begin
assign tx_status_s = tx_status[7:0]; assign tx_status_s = tx_ready_s[7:0];
end end
endgenerate endgenerate
generate generate
if (PCORE_NUM_OF_RX_LANES < 8) begin if (PCORE_NUM_OF_RX_LANES < 8) begin
assign rx_status_s[7:PCORE_NUM_OF_RX_LANES] = status_s[7:PCORE_NUM_OF_RX_LANES]; assign rx_status_s[7:PCORE_NUM_OF_RX_LANES] = status_s[7:PCORE_NUM_OF_RX_LANES];
assign rx_status_s[(PCORE_NUM_OF_RX_LANES-1):0] = rx_status; assign rx_status_s[(PCORE_NUM_OF_RX_LANES-1):0] = rx_ready_s;
end else begin end else begin
assign rx_status_s = rx_status[7:0]; assign rx_status_s = rx_ready_s[7:0];
end end
endgenerate endgenerate
// processor genvar n;
generate
for (n = 0; n < PCORE_NUM_OF_RX_LANES; n = n + 1) begin: g_rx_lane
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof_s),
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
.rx_sof (rx_sof[n]),
.rx_data (rx_data[n*32+31:n*32]));
end
endgenerate
up_xcvr #(.PCORE_ID(PCORE_ID), .PCORE_DEVICE_TYPE(PCORE_DEVICE_TYPE)) i_up_xcvr ( generate
for (n = 0; n < PCORE_NUM_OF_TX_LANES; n = n + 1) begin: g_tx_lane
assign tx_ip_data_s[((n*32) + 31):((n*32) + 24)] = tx_data[((n*32) + 7):((n*32) + 0)];
assign tx_ip_data_s[((n*32) + 23):((n*32) + 16)] = tx_data[((n*32) + 15):((n*32) + 8)];
assign tx_ip_data_s[((n*32) + 15):((n*32) + 8)] = tx_data[((n*32) + 23):((n*32) + 16)];
assign tx_ip_data_s[((n*32) + 7):((n*32) + 0)] = tx_data[((n*32) + 31):((n*32) + 24)];
end
endgenerate
sys_xcvr #(
.PCORE_NUM_OF_TX_LANES (PCORE_NUM_OF_TX_LANES),
.PCORE_NUM_OF_RX_LANES (PCORE_NUM_OF_RX_LANES),
.PCORE_ST_DATA_WIDTH (PCORE_ST_DATA_WIDTH),
.PCORE_ST_TRIGGER_WIDTH (PCORE_ST_TRIGGER_WIDTH))
i_sys_xcvr (
.up_clk (up_clk),
.up_rstn (up_rstn),
.rx_ref_clk (rx_ref_clk),
.rx_d (rx_d),
.tx_ref_clk (tx_ref_clk),
.tx_d (tx_d),
.rst (rst), .rst (rst),
.rx_clk (rx_clk), .rx_clk (rx_clk),
.rx_rst (rx_rst), .rx_rstn (rx_rstn),
.rx_sysref (rx_sysref_s),
.rx_ip_sync (rx_ip_sync_s),
.rx_ip_sof (rx_ip_sof_s),
.rx_ip_data (rx_ip_data_s),
.rx_ready (rx_ready_s),
.rx_int (),
.tx_clk (tx_clk),
.tx_rstn (tx_rstn),
.tx_sysref (tx_sysref_s),
.tx_ip_sync (tx_ip_sync_s),
.tx_ip_data (tx_ip_data_s),
.tx_ready (tx_ready_s),
.tx_int (),
.stp_clk (stp_clk),
.stp_data (stp_data),
.stp_trigger (stp_trigger));
// processor
up_xcvr #(
.PCORE_ID(PCORE_ID),
.PCORE_DEVICE_TYPE(PCORE_DEVICE_TYPE))
i_up_xcvr (
.rst (rst),
.rx_clk (rx_clk),
.rx_rstn (rx_rstn),
.rx_ext_sysref (rx_ext_sysref), .rx_ext_sysref (rx_ext_sysref),
.rx_sysref (rx_sysref), .rx_sysref (rx_sysref_s),
.rx_ip_sync (rx_ip_sync), .rx_ip_sync (rx_ip_sync_s),
.rx_sync (rx_sync), .rx_sync (rx_sync),
.rx_status (rx_status_s), .rx_status (rx_status_s),
.tx_clk (tx_clk), .tx_clk (tx_clk),
.tx_rst (tx_rst), .tx_rstn (tx_rstn),
.tx_ext_sysref (tx_ext_sysref), .tx_ext_sysref (tx_ext_sysref),
.tx_sysref (tx_sysref), .tx_sysref (tx_sysref_s),
.tx_sync (tx_sync), .tx_sync (tx_sync),
.tx_ip_sync (tx_ip_sync), .tx_ip_sync (tx_ip_sync_s),
.tx_status (tx_status_s), .tx_status (tx_status_s),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),

57
library/axi_jesd_xcvr/axi_jesd_xcvr_hw.tcl
View File

@ -14,6 +14,7 @@ set_module_property DISPLAY_NAME axi_jesd_xcvr
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_jesd_xcvr set_fileset_property quartus_synth TOP_LEVEL axi_jesd_xcvr
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
add_fileset_file ad_jesd_align.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_jesd_align.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file up_xcvr.v VERILOG PATH $ad_hdl_dir/library/common/up_xcvr.v add_fileset_file up_xcvr.v VERILOG PATH $ad_hdl_dir/library/common/up_xcvr.v
add_fileset_file axi_jesd_xcvr.v VERILOG PATH axi_jesd_xcvr.v TOP_LEVEL_FILE add_fileset_file axi_jesd_xcvr.v VERILOG PATH axi_jesd_xcvr.v TOP_LEVEL_FILE
@ -49,6 +50,20 @@ set_parameter_property PCORE_NUM_OF_RX_LANES TYPE INTEGER
set_parameter_property PCORE_NUM_OF_RX_LANES UNITS None set_parameter_property PCORE_NUM_OF_RX_LANES UNITS None
set_parameter_property PCORE_NUM_OF_RX_LANES HDL_PARAMETER true set_parameter_property PCORE_NUM_OF_RX_LANES HDL_PARAMETER true
add_parameter PCORE_ST_DATA_WIDTH INTEGER 0
set_parameter_property PCORE_ST_DATA_WIDTH DEFAULT_VALUE 32
set_parameter_property PCORE_ST_DATA_WIDTH DISPLAY_NAME PCORE_ST_DATA_WIDTH
set_parameter_property PCORE_ST_DATA_WIDTH TYPE INTEGER
set_parameter_property PCORE_ST_DATA_WIDTH UNITS None
set_parameter_property PCORE_ST_DATA_WIDTH HDL_PARAMETER true
add_parameter PCORE_ST_TRIGGER_WIDTH INTEGER 0
set_parameter_property PCORE_ST_TRIGGER_WIDTH DEFAULT_VALUE 32
set_parameter_property PCORE_ST_TRIGGER_WIDTH DISPLAY_NAME PCORE_ST_TRIGGER_WIDTH
set_parameter_property PCORE_ST_TRIGGER_WIDTH TYPE INTEGER
set_parameter_property PCORE_ST_TRIGGER_WIDTH UNITS None
set_parameter_property PCORE_ST_TRIGGER_WIDTH HDL_PARAMETER true
# axi4 slave # axi4 slave
add_interface s_axi_clock clock end add_interface s_axi_clock clock end
@ -83,35 +98,29 @@ add_interface_port s_axi s_axi_rready rready Input 1
# transceiver interface # transceiver interface
add_interface if_rst reset source ad_alt_intf clock rx_ref_clk input 1
set_interface_property if_rst associatedClock s_axi_clock ad_alt_intf signal rx_d input 4
add_interface_port if_rst rst reset Output 1 ad_alt_intf clock rx_clk output 1
add_interface if_rx_clk clock end
add_interface_port if_rx_clk rx_clk clk Input 1
add_interface if_rx_rst reset source
set_interface_property if_rx_rst associatedClock if_rx_clk
add_interface_port if_rx_rst rx_rst reset Output 1
ad_alt_intf signal rx_ext_sysref input 1 ad_alt_intf signal rx_ext_sysref input 1
ad_alt_intf signal rx_sysref output 1 export
ad_alt_intf signal rx_ip_sync input 1 export
ad_alt_intf signal rx_sync output 1 ad_alt_intf signal rx_sync output 1
ad_alt_intf signal rx_status input PCORE_NUM_OF_RX_LANES rx_ready ad_alt_intf signal rx_sof output PCORE_NUM_OF_RX_LANES
ad_alt_intf signal rx_data output PCORE_NUM_OF_RX_LANES*32
add_interface if_tx_clk clock end
add_interface_port if_tx_clk tx_clk clk Input 1
add_interface if_tx_rst reset source
set_interface_property if_tx_rst associatedClock if_tx_clk
add_interface_port if_tx_rst tx_rst reset Output 1
ad_alt_intf clock tx_ref_clk input 1
ad_alt_intf signal tx_d output 4
ad_alt_intf clock tx_clk output 1
ad_alt_intf signal tx_ext_sysref input 1 ad_alt_intf signal tx_ext_sysref input 1
ad_alt_intf signal tx_sysref output 1 export
ad_alt_intf signal tx_sync input 1 ad_alt_intf signal tx_sync input 1
ad_alt_intf signal tx_ip_sync output 1 export ad_alt_intf signal tx_data input PCORE_NUM_OF_TX_LANES*32
ad_alt_intf signal tx_status input PCORE_NUM_OF_TX_LANES tx_ready
# signal tap interface
ad_alt_intf clock stp_clk output 1
add_interface if_stp conduit source
add_interface_port if_stp stp_data acq_data_in output PCORE_ST_DATA_WIDTH
add_interface_port if_stp stp_trigger acq_trigger_in output PCORE_ST_TRIGGER_WIDTH
set_interface_property if_stp associatedClock if_stp_clk

38
library/common/up_xcvr.v
View File

@ -46,7 +46,7 @@ module up_xcvr (
// receive interface // receive interface
rx_clk, rx_clk,
rx_rst, rx_rstn,
rx_ext_sysref, rx_ext_sysref,
rx_sysref, rx_sysref,
rx_ip_sync, rx_ip_sync,
@ -56,7 +56,7 @@ module up_xcvr (
// transmit interface // transmit interface
tx_clk, tx_clk,
tx_rst, tx_rstn,
tx_ext_sysref, tx_ext_sysref,
tx_sysref, tx_sysref,
tx_sync, tx_sync,
@ -89,7 +89,7 @@ module up_xcvr (
// receive interface // receive interface
input rx_clk; input rx_clk;
output rx_rst; output rx_rstn;
input rx_ext_sysref; input rx_ext_sysref;
output rx_sysref; output rx_sysref;
input rx_ip_sync; input rx_ip_sync;
@ -99,7 +99,7 @@ module up_xcvr (
// transmit interface // transmit interface
input tx_clk; input tx_clk;
output tx_rst; output tx_rstn;
input tx_ext_sysref; input tx_ext_sysref;
output tx_sysref; output tx_sysref;
input tx_sync; input tx_sync;
@ -122,17 +122,22 @@ module up_xcvr (
// internal registers // internal registers
reg up_reset = 'd1; reg up_reset = 'd1;
reg up_rx_reset = 'd1;
reg up_tx_reset = 'd1;
reg up_wack = 'd0; reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0; reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0; reg up_resetn = 'd0;
reg up_rx_sysref_sel = 'd0; reg up_rx_sysref_sel = 'd0;
reg up_rx_sysref = 'd0; reg up_rx_sysref = 'd0;
reg up_rx_sync = 'd0; reg up_rx_sync = 'd0;
reg up_rx_resetn = 'd0;
reg up_tx_sysref_sel = 'd0; reg up_tx_sysref_sel = 'd0;
reg up_tx_sysref = 'd0; reg up_tx_sysref = 'd0;
reg up_tx_sync = 'd0; reg up_tx_sync = 'd0;
reg up_tx_resetn = 'd0;
reg up_rack = 'd0; reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata = 'd0;
reg rx_rstn = 'd0;
reg rx_sysref_sel_m1 = 'd0; reg rx_sysref_sel_m1 = 'd0;
reg rx_sysref_sel = 'd0; reg rx_sysref_sel = 'd0;
reg rx_up_sysref_m1 = 'd0; reg rx_up_sysref_m1 = 'd0;
@ -141,6 +146,7 @@ module up_xcvr (
reg rx_up_sync_m1 = 'd0; reg rx_up_sync_m1 = 'd0;
reg rx_up_sync = 'd0; reg rx_up_sync = 'd0;
reg rx_sync = 'd0; reg rx_sync = 'd0;
reg tx_rstn = 'd0;
reg tx_sysref_sel_m1 = 'd0; reg tx_sysref_sel_m1 = 'd0;
reg tx_sysref_sel = 'd0; reg tx_sysref_sel = 'd0;
reg tx_up_sysref_m1 = 'd0; reg tx_up_sysref_m1 = 'd0;
@ -156,6 +162,8 @@ module up_xcvr (
// internal signals // internal signals
wire rx_rst;
wire tx_rst;
wire up_wreq_s; wire up_wreq_s;
wire up_rreq_s; wire up_rreq_s;
@ -169,17 +177,23 @@ module up_xcvr (
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_reset <= 1'b1; up_reset <= 1'b1;
up_rx_reset <= 1'b1;
up_tx_reset <= 1'b1;
up_wack <= 'd0; up_wack <= 'd0;
up_scratch <= 'd0; up_scratch <= 'd0;
up_resetn <= 'd0; up_resetn <= 'd0;
up_rx_sysref_sel <= 'd0; up_rx_sysref_sel <= 'd0;
up_rx_sysref <= 'd0; up_rx_sysref <= 'd0;
up_rx_sync <= 'd0; up_rx_sync <= 'd0;
up_rx_resetn <= 'd0;
up_tx_sysref_sel <= 'd0; up_tx_sysref_sel <= 'd0;
up_tx_sysref <= 'd0; up_tx_sysref <= 'd0;
up_tx_sync <= 'd0; up_tx_sync <= 'd0;
up_tx_resetn <= 'd0;
end else begin end else begin
up_reset <= ~up_resetn; up_reset <= ~up_resetn;
up_rx_reset <= ~(up_resetn & up_rx_resetn);
up_tx_reset <= ~(up_resetn & up_tx_resetn);
up_wack <= up_wreq_s; up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata; up_scratch <= up_wdata;
@ -194,6 +208,9 @@ module up_xcvr (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_rx_sync <= up_wdata[0]; up_rx_sync <= up_wdata[0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_rx_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tx_sysref_sel <= up_wdata[1]; up_tx_sysref_sel <= up_wdata[1];
up_tx_sysref <= up_wdata[0]; up_tx_sysref <= up_wdata[0];
@ -201,6 +218,9 @@ module up_xcvr (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_tx_sync <= up_wdata[0]; up_tx_sync <= up_wdata[0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tx_resetn <= up_wdata[0];
end
end end
end end
@ -221,9 +241,11 @@ module up_xcvr (
8'h10: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref}; 8'h10: up_rdata <= {30'd0, up_rx_sysref_sel, up_rx_sysref};
8'h11: up_rdata <= {31'd0, up_rx_sync}; 8'h11: up_rdata <= {31'd0, up_rx_sync};
8'h12: up_rdata <= {23'd0, up_rx_status}; 8'h12: up_rdata <= {23'd0, up_rx_status};
8'h13: up_rdata <= {31'd0, up_rx_resetn};
8'h20: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref}; 8'h20: up_rdata <= {30'd0, up_tx_sysref_sel, up_tx_sysref};
8'h21: up_rdata <= {31'd0, up_tx_sync}; 8'h21: up_rdata <= {31'd0, up_tx_sync};
8'h22: up_rdata <= {23'd0, up_tx_status}; 8'h22: up_rdata <= {23'd0, up_tx_status};
8'h23: up_rdata <= {31'd0, up_tx_resetn};
8'h30: up_rdata <= PCORE_DEVICE_TYPE; 8'h30: up_rdata <= PCORE_DEVICE_TYPE;
default: up_rdata <= 0; default: up_rdata <= 0;
endcase endcase
@ -237,13 +259,14 @@ module up_xcvr (
assign rst = up_reset; assign rst = up_reset;
ad_rst i_rx_rst_reg (.preset(up_reset), .clk(rx_clk), .rst(rx_rst)); ad_rst i_rx_rst_reg (.preset(up_rx_reset), .clk(rx_clk), .rst(rx_rst));
ad_rst i_tx_rst_reg (.preset(up_reset), .clk(tx_clk), .rst(tx_rst)); ad_rst i_tx_rst_reg (.preset(up_tx_reset), .clk(tx_clk), .rst(tx_rst));
// rx sysref & sync // rx sysref & sync
always @(posedge rx_clk or posedge rx_rst) begin always @(posedge rx_clk or posedge rx_rst) begin
if (rx_rst == 1'b1) begin if (rx_rst == 1'b1) begin
rx_rstn <= 'd0;
rx_sysref_sel_m1 <= 'd0; rx_sysref_sel_m1 <= 'd0;
rx_sysref_sel <= 'd0; rx_sysref_sel <= 'd0;
rx_up_sysref_m1 <= 'd0; rx_up_sysref_m1 <= 'd0;
@ -253,6 +276,7 @@ module up_xcvr (
rx_up_sync <= 'd0; rx_up_sync <= 'd0;
rx_sync <= 'd0; rx_sync <= 'd0;
end else begin end else begin
rx_rstn <= 1'd1;
rx_sysref_sel_m1 <= up_rx_sysref_sel; rx_sysref_sel_m1 <= up_rx_sysref_sel;
rx_sysref_sel <= rx_sysref_sel_m1; rx_sysref_sel <= rx_sysref_sel_m1;
rx_up_sysref_m1 <= up_rx_sysref; rx_up_sysref_m1 <= up_rx_sysref;
@ -272,6 +296,7 @@ module up_xcvr (
always @(posedge tx_clk or posedge tx_rst) begin always @(posedge tx_clk or posedge tx_rst) begin
if (tx_rst == 1'b1) begin if (tx_rst == 1'b1) begin
tx_rstn <= 'd0;
tx_sysref_sel_m1 <= 'd0; tx_sysref_sel_m1 <= 'd0;
tx_sysref_sel <= 'd0; tx_sysref_sel <= 'd0;
tx_up_sysref_m1 <= 'd0; tx_up_sysref_m1 <= 'd0;
@ -281,6 +306,7 @@ module up_xcvr (
tx_up_sync <= 'd0; tx_up_sync <= 'd0;
tx_ip_sync <= 'd0; tx_ip_sync <= 'd0;
end else begin end else begin
tx_rstn <= 1'd1;
tx_sysref_sel_m1 <= up_tx_sysref_sel; tx_sysref_sel_m1 <= up_tx_sysref_sel;
tx_sysref_sel <= tx_sysref_sel_m1; tx_sysref_sel <= tx_sysref_sel_m1;
tx_up_sysref_m1 <= up_tx_sysref; tx_up_sysref_m1 <= up_tx_sysref;