common/a10soc: Bridge support
parent
f0b753321a
commit
6e6c51dd27
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@ -195,10 +195,25 @@ proc ad_cpu_interrupt {m_irq m_port} {
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set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
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}
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proc ad_cpu_interconnect {m_base m_port} {
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proc ad_cpu_interconnect {m_base m_port {avl_bridge ""} {avl_bridge_base 0x00000000} {avl_address_width 18}} {
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add_connection sys_hps.h2f_lw_axi_master ${m_port}
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set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
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if {[string equal ${avl_bridge} ""]} {
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add_connection sys_hps.h2f_lw_axi_master ${m_port}
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set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
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} else {
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if {[lsearch -exact [get_instances] ${avl_bridge}] == -1} {
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## Instantiate the bridge and connect the interfaces
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add_instance ${avl_bridge} altera_avalon_mm_bridge
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set_instance_parameter_value ${avl_bridge} {ADDRESS_WIDTH} $avl_address_width
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set_instance_parameter_value ${avl_bridge} {SYNC_RESET} {1}
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add_connection sys_hps.h2f_lw_axi_master ${avl_bridge}.s0
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set_connection_parameter_value sys_hps.h2f_lw_axi_master/${avl_bridge}.s0 baseAddress ${avl_bridge_base}
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add_connection sys_clk.clk ${avl_bridge}.clk
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add_connection sys_clk.clk_reset ${avl_bridge}.reset
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}
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add_connection ${avl_bridge}.m0 ${m_port}
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set_connection_parameter_value ${avl_bridge}.m0/${m_port} baseAddress ${m_base}
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}
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}
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proc ad_dma_interconnect {m_port} {
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