diff --git a/projects/adv7511/ac701/Makefile b/projects/adv7511/ac701/Makefile deleted file mode 100644 index 5240a5fb1..000000000 --- a/projects/adv7511/ac701/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := adv7511_ac701 - -M_DEPS += ../../common/ac701/ac701_system_mig.prj -M_DEPS += ../../common/ac701/ac701_system_constr.xdc -M_DEPS += ../../common/ac701/ac701_system_bd.tcl -M_DEPS += ../../adv7511/common/adv7511_bd.tcl -M_DEPS += ../../adv7511/ac701/system_constr.xdc -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v - -LIB_DEPS += axi_clkgen -LIB_DEPS += axi_hdmi_tx -LIB_DEPS += axi_spdif_tx - -include ../../scripts/project-xilinx.mk diff --git a/projects/adv7511/ac701/system_bd.tcl b/projects/adv7511/ac701/system_bd.tcl deleted file mode 100644 index 892844d69..000000000 --- a/projects/adv7511/ac701/system_bd.tcl +++ /dev/null @@ -1,7 +0,0 @@ - -source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl -source $ad_hdl_dir/projects/adv7511/common/adv7511_bd.tcl - -ad_ip_parameter axi_hdmi_dma CONFIG.c_m_axi_mm2s_data_width 512 -ad_ip_parameter axi_hdmi_dma CONFIG.c_m_axis_mm2s_tdata_width 64 - diff --git a/projects/adv7511/ac701/system_constr.xdc b/projects/adv7511/ac701/system_constr.xdc deleted file mode 100644 index 7bbc40685..000000000 --- a/projects/adv7511/ac701/system_constr.xdc +++ /dev/null @@ -1,36 +0,0 @@ - -# hdmi - -set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk] -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS18} [get_ports hdmi_hsync] -set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS18} [get_ports hdmi_vsync] -set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS18} [get_ports hdmi_data_e] -set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[0]] -set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[1]] -set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[2]] -set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[3]] -set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[4]] -set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[5]] -set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[6]] -set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[7]] -set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[8]] -set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[9]] -set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[10]] -set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[11]] -set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[12]] -set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[13]] -set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[14]] -set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[15]] -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[16]] -set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[17]] -set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[18]] -set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[19]] -set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[20]] -set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[21]] -set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[22]] -set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[23]] - -# spdif - -set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS18} [get_ports spdif] - diff --git a/projects/adv7511/ac701/system_project.tcl b/projects/adv7511/ac701/system_project.tcl deleted file mode 100644 index 08f4f4093..000000000 --- a/projects/adv7511/ac701/system_project.tcl +++ /dev/null @@ -1,14 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_xilinx adv7511_ac701 -adi_project_files adv7511_ac701 [list \ - "system_top.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" \ - "$ad_hdl_dir/projects/adv7511/ac701/system_constr.xdc"] - -adi_project_run adv7511_ac701 - diff --git a/projects/adv7511/ac701/system_top.v b/projects/adv7511/ac701/system_top.v deleted file mode 100644 index 4acff105d..000000000 --- a/projects/adv7511/ac701/system_top.v +++ /dev/null @@ -1,164 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - input sys_rst, - input sys_clk_p, - input sys_clk_n, - - input uart_sin, - output uart_sout, - - output [13:0] ddr3_addr, - output [ 2:0] ddr3_ba, - output ddr3_cas_n, - output [ 0:0] ddr3_ck_n, - output [ 0:0] ddr3_ck_p, - output [ 0:0] ddr3_cke, - output [ 0:0] ddr3_cs_n, - output [ 7:0] ddr3_dm, - inout [63:0] ddr3_dq, - inout [ 7:0] ddr3_dqs_n, - inout [ 7:0] ddr3_dqs_p, - output [ 0:0] ddr3_odt, - output ddr3_ras_n, - output ddr3_reset_n, - output ddr3_we_n, - - output phy_reset_n, - output phy_mdc, - inout phy_mdio, - output phy_tx_clk, - output phy_tx_ctrl, - output [ 3:0] phy_tx_data, - input phy_rx_clk, - input phy_rx_ctrl, - input [ 3:0] phy_rx_data, - - output fan_pwm, - - inout [ 6:0] gpio_lcd, - inout [12:0] gpio_bd, - - output iic_rstn, - inout iic_scl, - inout iic_sda, - - output hdmi_out_clk, - output hdmi_hsync, - output hdmi_vsync, - output hdmi_data_e, - output [23:0] hdmi_data, - - output spdif); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - - // default logic - - assign mgt_clk_sel = 2'd0; - assign fan_pwm = 1'b1; - assign iic_rstn = 1'b1; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_sw_led ( - .dio_t (gpio_t[12:0]), - .dio_i (gpio_o[12:0]), - .dio_o (gpio_i[12:0]), - .dio_p (gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr3_addr (ddr3_addr), - .ddr3_ba (ddr3_ba), - .ddr3_cas_n (ddr3_cas_n), - .ddr3_ck_n (ddr3_ck_n), - .ddr3_ck_p (ddr3_ck_p), - .ddr3_cke (ddr3_cke), - .ddr3_cs_n (ddr3_cs_n), - .ddr3_dm (ddr3_dm), - .ddr3_dq (ddr3_dq), - .ddr3_dqs_n (ddr3_dqs_n), - .ddr3_dqs_p (ddr3_dqs_p), - .ddr3_odt (ddr3_odt), - .ddr3_ras_n (ddr3_ras_n), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_we_n (ddr3_we_n), - .gpio_lcd_tri_io (gpio_lcd), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio0_i (gpio_i[31:0]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32]), - .gpio1_i (gpio_i[63:32]), - .hdmi_24_data (hdmi_data), - .hdmi_24_data_e (hdmi_data_e), - .hdmi_24_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_24_vsync (hdmi_vsync), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .mb_intr_06 (1'b0), - .mb_intr_12 (1'b0), - .mb_intr_13 (1'b0), - .mb_intr_14 (1'b0), - .mb_intr_15 (1'b0), - .mdio_mdio_io (phy_mdio), - .mdio_mdc (phy_mdc), - .phy_rst_n (phy_reset_n), - .rgmii_rd (phy_rx_data), - .rgmii_rx_ctl (phy_rx_ctrl), - .rgmii_rxc (phy_rx_clk), - .rgmii_td (phy_tx_data), - .rgmii_tx_ctl (phy_tx_ctrl), - .rgmii_txc (phy_tx_clk), - .spdif (spdif), - .sys_clk_n (sys_clk_n), - .sys_clk_p (sys_clk_p), - .sys_rst (sys_rst), - .uart_sin (uart_sin), - .uart_sout (uart_sout)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/adv7511/mitx045/Makefile b/projects/adv7511/mitx045/Makefile deleted file mode 100644 index 0cf2d256f..000000000 --- a/projects/adv7511/mitx045/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := adv7511_mitx045 - -M_DEPS += ../../common/mitx045/mitx045_system_ps7.tcl -M_DEPS += ../../common/mitx045/mitx045_system_constr.xdc -M_DEPS += ../../common/mitx045/mitx045_system_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v - -LIB_DEPS += axi_clkgen -LIB_DEPS += axi_hdmi_tx -LIB_DEPS += axi_i2s_adi -LIB_DEPS += axi_spdif_tx - -include ../../scripts/project-xilinx.mk diff --git a/projects/adv7511/mitx045/system_bd.tcl b/projects/adv7511/mitx045/system_bd.tcl deleted file mode 100644 index 9125cfcd5..000000000 --- a/projects/adv7511/mitx045/system_bd.tcl +++ /dev/null @@ -1,3 +0,0 @@ - -source $ad_hdl_dir/projects/common/mitx045/mitx045_system_bd.tcl - diff --git a/projects/adv7511/mitx045/system_project.tcl b/projects/adv7511/mitx045/system_project.tcl deleted file mode 100644 index 45f3c70a9..000000000 --- a/projects/adv7511/mitx045/system_project.tcl +++ /dev/null @@ -1,13 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_xilinx adv7511_mitx045 -adi_project_files adv7511_mitx045 [list \ - "system_top.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/mitx045/mitx045_system_constr.xdc"] - -adi_project_run adv7511_mitx045 - diff --git a/projects/adv7511/mitx045/system_top.v b/projects/adv7511/mitx045/system_top.v deleted file mode 100644 index d4de5a830..000000000 --- a/projects/adv7511/mitx045/system_top.v +++ /dev/null @@ -1,154 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [11:0] gpio_bd, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [15:0] hdmi_data, - - output spdif, - - output i2s_mclk, - output i2s_bclk, - output i2s_lrclk, - output i2s_sdata_out, - input i2s_sdata_in, - - inout iic_scl, - inout iic_sda); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [19:0] gpio_wire; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(32)) i_iobuf ( - .dio_t (gpio_t[31:0]), - .dio_i (gpio_o[31:0]), - .dio_o (gpio_i[31:0]), - .dio_p ({ gpio_wire, - gpio_bd})); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .i2s_bclk (i2s_bclk), - .i2s_lrclk (i2s_lrclk), - .i2s_mclk (i2s_mclk), - .i2s_sdata_in (i2s_sdata_in), - .i2s_sdata_out (i2s_sdata_out), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_10 (1'b0), - .ps_intr_11 (1'b0), - .ps_intr_12 (1'b0), - .ps_intr_13 (1'b0), - .spdif (spdif)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/cn0363/microzed/Makefile b/projects/cn0363/microzed/Makefile deleted file mode 100644 index 048fa2fea..000000000 --- a/projects/cn0363/microzed/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := cn0363_microzed - -M_DEPS += ../common/cn0363_bd.tcl -M_DEPS += ../../common/microzed/microzed_system_ps7.tcl -M_DEPS += ../../common/microzed/microzed_system_constr.xdc -M_DEPS += ../../common/microzed/microzed_system_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v - -LIB_DEPS += axi_dmac -LIB_DEPS += axi_generic_adc -LIB_DEPS += cn0363/cn0363_dma_sequencer -LIB_DEPS += cn0363/cn0363_phase_data_sync -LIB_DEPS += cordic_demod -LIB_DEPS += spi_engine/axi_spi_engine -LIB_DEPS += spi_engine/spi_engine_execution -LIB_DEPS += spi_engine/spi_engine_interconnect -LIB_DEPS += spi_engine/spi_engine_offload -LIB_DEPS += util_axis_resize -LIB_DEPS += util_sigma_delta_spi - -include ../../scripts/project-xilinx.mk diff --git a/projects/cn0363/microzed/system_bd.tcl b/projects/cn0363/microzed/system_bd.tcl deleted file mode 100644 index 6c09795d3..000000000 --- a/projects/cn0363/microzed/system_bd.tcl +++ /dev/null @@ -1,3 +0,0 @@ - -source $ad_hdl_dir/projects/common/microzed/microzed_system_bd.tcl -source ../common/cn0363_bd.tcl diff --git a/projects/cn0363/microzed/system_constr.xdc b/projects/cn0363/microzed/system_constr.xdc deleted file mode 100644 index 0816b1b0a..000000000 --- a/projects/cn0363/microzed/system_constr.xdc +++ /dev/null @@ -1,23 +0,0 @@ - -# PL PMOD - -set_property PACKAGE_PIN G17 [get_ports gain0_o] -set_property IOSTANDARD LVCMOS33 [get_ports gain0_o] -set_property PACKAGE_PIN G18 [get_ports gain1_o] -set_property IOSTANDARD LVCMOS33 [get_ports gain1_o] -set_property PACKAGE_PIN F19 [get_ports {spi_cs[1]}] -set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[1]}] -set_property PACKAGE_PIN F20 [get_ports led_clk_o] -set_property IOSTANDARD LVCMOS33 [get_ports led_clk_o] - -set_property PACKAGE_PIN N15 [get_ports {spi_cs[0]}] -set_property IOSTANDARD LVCMOS33 [get_ports {spi_cs[0]}] -set_property PACKAGE_PIN N16 [get_ports spi_sdo] -set_property IOSTANDARD LVCMOS33 [get_ports spi_sdo] -set_property PULLUP true [get_ports spi_sdo] -set_property PACKAGE_PIN L14 [get_ports spi_sdi] -set_property IOSTANDARD LVCMOS33 [get_ports spi_sdi] -set_property PULLUP true [get_ports spi_sdi] -set_property PACKAGE_PIN L15 [get_ports spi_sclk] -set_property IOSTANDARD LVCMOS33 [get_ports spi_sclk] - diff --git a/projects/cn0363/microzed/system_project.tcl b/projects/cn0363/microzed/system_project.tcl deleted file mode 100644 index 7a9ee67ff..000000000 --- a/projects/cn0363/microzed/system_project.tcl +++ /dev/null @@ -1,12 +0,0 @@ -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_xilinx cn0363_microzed -adi_project_files cn0363_microzed [list \ - "system_top.v" \ - "system_constr.xdc" \ - "$ad_hdl_dir/projects/common/microzed/microzed_system_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] - -adi_project_run cn0363_microzed diff --git a/projects/cn0363/microzed/system_top.v b/projects/cn0363/microzed/system_top.v deleted file mode 100644 index cfdcb7d67..000000000 --- a/projects/cn0363/microzed/system_top.v +++ /dev/null @@ -1,166 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout spi_sdo, - input spi_sdi, - output [ 1:0] spi_cs, - output spi_sclk, - output led_clk_o, - output gain0_o, - output gain1_o, - - input otg_vbusoc); - - // internal signals - - wire [34:0] gpio_i; - wire [34:0] gpio_o; - wire [34:0] gpio_t; - wire [23:0] offload_sdi_data; - - wire spi_sdo_o; - wire spi_sdo_t; - wire excitation; - - assign gain0_o = gpio_o[32]; - assign gain1_o = gpio_o[33]; - - assign gpio_i[34] = spi_sdi; // Interrupt - assign gpio_i[33:0] = gpio_o[33:0]; - assign led_clk_o = excitation; - - ad_iobuf #( - .DATA_WIDTH(1) - ) i_sdo_iobuf ( - .dio_t(spi_sdo_t), - .dio_i(spi_sdo_o), - .dio_o(), - .dio_p(spi_sdo) - ); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_11 (1'b0), - .ps_intr_14 (1'b0), - .ps_intr_15 (1'b0), - .ps_intr_10 (1'b0), - .spi0_clk_i (1'b0), - .spi0_clk_o (), - .spi0_csn_0_o (), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (), - .spi1_clk_i (1'b0), - .spi1_clk_o (), - .spi1_csn_0_o (), - .spi1_csn_1_o (), - .spi1_csn_2_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (1'b0), - .spi1_sdo_o (), - .spi_sdo (spi_sdo_o), - .spi_sdo_t (spi_sdo_t), - .spi_sdi (spi_sdi), - .spi_cs (spi_cs), - .spi_sclk (spi_sclk), - .excitation (excitation)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/de10/Makefile b/projects/de10/Makefile deleted file mode 100644 index 3ecc99bad..000000000 --- a/projects/de10/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := de10nano - - -LIB_DEPS += axi_dmac -LIB_DEPS += axi_hdmi_tx - -include ../scripts/project-altera.mk diff --git a/projects/de10/system_constr.sdc b/projects/de10/system_constr.sdc deleted file mode 100644 index b2953bd0a..000000000 --- a/projects/de10/system_constr.sdc +++ /dev/null @@ -1,6 +0,0 @@ - -create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}] - -derive_pll_clocks -derive_clock_uncertainty - diff --git a/projects/de10/system_project.tcl b/projects/de10/system_project.tcl deleted file mode 100644 index d205905bb..000000000 --- a/projects/de10/system_project.tcl +++ /dev/null @@ -1,786 +0,0 @@ - -source ../scripts/adi_env.tcl -source ../scripts/adi_project_alt.tcl - -adi_project_altera de10nano - -# clocks (V11, Y13, E11 - PL 50MHz) -# clocks (E20, D20 - HPS 25MHz) - -set_location_assignment PIN_V11 -to sys_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sys_clk - -# leds - -set_location_assignment PIN_W15 -to gpio_bd[0] -set_location_assignment PIN_AA24 -to gpio_bd[1] -set_location_assignment PIN_V16 -to gpio_bd[2] -set_location_assignment PIN_V15 -to gpio_bd[3] -set_location_assignment PIN_AF26 -to gpio_bd[4] -set_location_assignment PIN_AE26 -to gpio_bd[5] -set_location_assignment PIN_Y16 -to gpio_bd[6] -set_location_assignment PIN_AA23 -to gpio_bd[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[7] - -# dip switches - -set_location_assignment PIN_Y24 -to gpio_bd[8] -set_location_assignment PIN_W24 -to gpio_bd[9] -set_location_assignment PIN_W21 -to gpio_bd[10] -set_location_assignment PIN_W20 -to gpio_bd[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[11] - -# push-buttons - -set_location_assignment PIN_AH17 -to gpio_bd[12] -set_location_assignment PIN_AH16 -to gpio_bd[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_bd[13] - -# hps gpio - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_led -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hps_gpio_pb - -# uart - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_rx -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart0_tx -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to uart0_rx -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to uart0_tx - -# usb - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_stp -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_dir -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_nxt -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to usb1_d[7] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_clk -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_stp -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_dir -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_nxt -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to usb1_d[7] - -# sdio - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_cmd -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdio_d[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sdio_clk -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sdio_cmd -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sdio_d[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sdio_d[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sdio_d[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to sdio_d[3] - -# qspi - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_ss0 -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to qspi_io[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to qspi_ss0 -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to qspi_clk -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to qspi_io[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to qspi_io[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to qspi_io[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to qspi_io[3] - -# ethernet - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_ctl -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_tx_d[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_ctl -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_rx_d[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdc -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to eth1_mdio -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_clk -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_ctl -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_d[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_d[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_d[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_tx_d[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_clk -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_ctl -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_d[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_d[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_d[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_rx_d[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_mdc -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to eth1_mdio - -# gpio-0 (JP1) - -set_location_assignment PIN_V12 -to gpio_0[0] -set_location_assignment PIN_E8 -to gpio_0[1] -set_location_assignment PIN_W12 -to gpio_0[2] -set_location_assignment PIN_D11 -to gpio_0[3] -set_location_assignment PIN_D8 -to gpio_0[4] -set_location_assignment PIN_AH13 -to gpio_0[5] -set_location_assignment PIN_AF7 -to gpio_0[6] -set_location_assignment PIN_AH14 -to gpio_0[7] -set_location_assignment PIN_AF4 -to gpio_0[8] -set_location_assignment PIN_AH3 -to gpio_0[9] -set_location_assignment PIN_AD5 -to gpio_0[10] -set_location_assignment PIN_AG14 -to gpio_0[11] -set_location_assignment PIN_AE23 -to gpio_0[12] -set_location_assignment PIN_AE6 -to gpio_0[13] -set_location_assignment PIN_AD23 -to gpio_0[14] -set_location_assignment PIN_AE24 -to gpio_0[15] -set_location_assignment PIN_D12 -to gpio_0[16] -set_location_assignment PIN_AD20 -to gpio_0[17] -set_location_assignment PIN_C12 -to gpio_0[18] -set_location_assignment PIN_AD17 -to gpio_0[19] -set_location_assignment PIN_AC23 -to gpio_0[20] -set_location_assignment PIN_AC22 -to gpio_0[21] -set_location_assignment PIN_Y19 -to gpio_0[22] -set_location_assignment PIN_AB23 -to gpio_0[23] -set_location_assignment PIN_AA19 -to gpio_0[24] -set_location_assignment PIN_W11 -to gpio_0[25] -set_location_assignment PIN_AA18 -to gpio_0[26] -set_location_assignment PIN_W14 -to gpio_0[27] -set_location_assignment PIN_Y18 -to gpio_0[28] -set_location_assignment PIN_Y17 -to gpio_0[29] -set_location_assignment PIN_AB25 -to gpio_0[30] -set_location_assignment PIN_AB26 -to gpio_0[31] -set_location_assignment PIN_Y11 -to gpio_0[32] -set_location_assignment PIN_AA26 -to gpio_0[33] -set_location_assignment PIN_AA13 -to gpio_0[34] -set_location_assignment PIN_AA11 -to gpio_0[35] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[18] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[19] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[20] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[21] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[22] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[23] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[24] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[25] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[26] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[27] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[28] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[29] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[30] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[31] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[32] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[33] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[34] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_0[35] - -# gpio-1 (JP7) - -set_location_assignment PIN_Y15 -to gpio_1[0] -set_location_assignment PIN_AC24 -to gpio_1[1] -set_location_assignment PIN_AA15 -to gpio_1[2] -set_location_assignment PIN_AD26 -to gpio_1[3] -set_location_assignment PIN_AG28 -to gpio_1[4] -set_location_assignment PIN_AF28 -to gpio_1[5] -set_location_assignment PIN_AE25 -to gpio_1[6] -set_location_assignment PIN_AF27 -to gpio_1[7] -set_location_assignment PIN_AG26 -to gpio_1[8] -set_location_assignment PIN_AH27 -to gpio_1[9] -set_location_assignment PIN_AG25 -to gpio_1[10] -set_location_assignment PIN_AH26 -to gpio_1[11] -set_location_assignment PIN_AH24 -to gpio_1[12] -set_location_assignment PIN_AF25 -to gpio_1[13] -set_location_assignment PIN_AG23 -to gpio_1[14] -set_location_assignment PIN_AF23 -to gpio_1[15] -set_location_assignment PIN_AG24 -to gpio_1[16] -set_location_assignment PIN_AH22 -to gpio_1[17] -set_location_assignment PIN_AH21 -to gpio_1[18] -set_location_assignment PIN_AG21 -to gpio_1[19] -set_location_assignment PIN_AH23 -to gpio_1[20] -set_location_assignment PIN_AA20 -to gpio_1[21] -set_location_assignment PIN_AF22 -to gpio_1[22] -set_location_assignment PIN_AE22 -to gpio_1[23] -set_location_assignment PIN_AG20 -to gpio_1[24] -set_location_assignment PIN_AF21 -to gpio_1[25] -set_location_assignment PIN_AG19 -to gpio_1[26] -set_location_assignment PIN_AH19 -to gpio_1[27] -set_location_assignment PIN_AG18 -to gpio_1[28] -set_location_assignment PIN_AH18 -to gpio_1[29] -set_location_assignment PIN_AF18 -to gpio_1[30] -set_location_assignment PIN_AF20 -to gpio_1[31] -set_location_assignment PIN_AG15 -to gpio_1[32] -set_location_assignment PIN_AE20 -to gpio_1[33] -set_location_assignment PIN_AE19 -to gpio_1[34] -set_location_assignment PIN_AE17 -to gpio_1[35] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[18] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[19] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[20] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[21] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[22] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[23] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[24] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[25] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[26] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[27] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[28] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[29] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[30] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[31] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[32] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[33] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[34] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to gpio_1[35] - -# arduino (JP2, JP3, JP4 & JP5) - -set_location_assignment PIN_AG13 -to arduino_gpio[0] -set_location_assignment PIN_AF13 -to arduino_gpio[1] -set_location_assignment PIN_AG10 -to arduino_gpio[2] -set_location_assignment PIN_AG9 -to arduino_gpio[3] -set_location_assignment PIN_U14 -to arduino_gpio[4] -set_location_assignment PIN_U13 -to arduino_gpio[5] -set_location_assignment PIN_AG8 -to arduino_gpio[6] -set_location_assignment PIN_AH8 -to arduino_spi_csn[3] -set_location_assignment PIN_AF17 -to arduino_spi_csn[2] -set_location_assignment PIN_AE15 -to arduino_spi_csn[1] -set_location_assignment PIN_AF15 -to arduino_spi_csn[0] -set_location_assignment PIN_AG16 -to arduino_spi_mosi -set_location_assignment PIN_AH11 -to arduino_spi_miso -set_location_assignment PIN_AH12 -to arduino_spi_clk -set_location_assignment PIN_AH9 -to arduino_i2c_sda -set_location_assignment PIN_AG11 -to arduino_i2c_scl -set_location_assignment PIN_AH7 -to arduino_reset_n -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_gpio[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_gpio[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_gpio[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_gpio[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_gpio[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_gpio[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_gpio[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_spi_csn[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_spi_csn[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_spi_csn[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_spi_csn[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_spi_mosi -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_spi_miso -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_spi_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_i2c_sda -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_i2c_scl -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to arduino_reset_n - -# adxl345 (i2c address 0xa6/0xa7) (i2c0) -# scl (C18), sda (A19) & int (A17) - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adxl345_scl -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adxl345_sda -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to adxl345_int - -# ltc connector (J17) -# i2c/spi select-gpio (H13,J17.14) (i2c1, spim1) -# sclk (K18,J17.4,J17.11), sda (A21,J17.7,J17.9) -# csn (C16,J17.6), clk (C19,J17.4), mosi (B16,J17.J17.7) & miso (B19,J17.5) - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc_i2c_spi_sel -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc_i2c_scl -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc_i2c_sda -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc_spi_csn -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc_spi_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc_spi_mosi -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ltc_spi_miso - -# HDMI - -set_location_assignment PIN_U10 -to hdmi_i2c_scl -set_location_assignment PIN_AA4 -to hdmi_i2c_sda -set_location_assignment PIN_T13 -to hdmi_i2s -set_location_assignment PIN_T11 -to hdmi_lrclk -set_location_assignment PIN_U11 -to hdmi_mclk -set_location_assignment PIN_T12 -to hdmi_sclk -set_location_assignment PIN_AG5 -to hdmi_out_clk -set_location_assignment PIN_AD12 -to hdmi_data[0] -set_location_assignment PIN_AE12 -to hdmi_data[1] -set_location_assignment PIN_W8 -to hdmi_data[2] -set_location_assignment PIN_Y8 -to hdmi_data[3] -set_location_assignment PIN_AD11 -to hdmi_data[4] -set_location_assignment PIN_AD10 -to hdmi_data[5] -set_location_assignment PIN_AE11 -to hdmi_data[6] -set_location_assignment PIN_Y5 -to hdmi_data[7] -set_location_assignment PIN_AF10 -to hdmi_data[8] -set_location_assignment PIN_Y4 -to hdmi_data[9] -set_location_assignment PIN_AE9 -to hdmi_data[10] -set_location_assignment PIN_AB4 -to hdmi_data[11] -set_location_assignment PIN_AE7 -to hdmi_data[12] -set_location_assignment PIN_AF6 -to hdmi_data[13] -set_location_assignment PIN_AF8 -to hdmi_data[14] -set_location_assignment PIN_AF5 -to hdmi_data[15] -set_location_assignment PIN_AE4 -to hdmi_data[16] -set_location_assignment PIN_AH2 -to hdmi_data[17] -set_location_assignment PIN_AH4 -to hdmi_data[18] -set_location_assignment PIN_AH5 -to hdmi_data[19] -set_location_assignment PIN_AH6 -to hdmi_data[20] -set_location_assignment PIN_AG6 -to hdmi_data[21] -set_location_assignment PIN_AF9 -to hdmi_data[22] -set_location_assignment PIN_AE8 -to hdmi_data[23] -set_location_assignment PIN_AD19 -to hdmi_data_e -set_location_assignment PIN_T8 -to hdmi_hsync -set_location_assignment PIN_V13 -to hdmi_vsync - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_i2c_scl -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_i2c_sda -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_i2s -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_lrclk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_mclk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_sclk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_out_clk -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[15] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[16] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[17] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[18] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[19] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[20] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[21] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[22] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data[23] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_data_e -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_hsync -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hdmi_vsync - -# ddr - -set_instance_assignment -name D5_DELAY 2 -to ddr3_ck_p -set_instance_assignment -name D5_DELAY 2 -to ddr3_ck_n - -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[7] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[8] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[9] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[10] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[11] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[12] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[13] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[14] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cas_n -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cke -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cs_n -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_odt -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ras_n -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_reset_n -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_we_n - -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[0].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[1].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[2].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uio_pads|dq_ddio[3].read_capture_clk_buffer -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[0] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[1] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[2] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_wraddress[3] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[0] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[1] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[2] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|uread_datapath|reset_n_fifo_write_side[3] -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_mem_stable_n -set_instance_assignment -name GLOBAL_SIGNAL OFF -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|p0|umemphy|ureset|phy_reset_n - -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[0] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[1] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[2] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[3] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[4] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[5] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[6] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[7] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[8] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[9] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[10] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[11] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[12] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[13] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[14] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[15] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[16] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[17] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[18] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[19] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[20] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[21] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[22] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[23] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[24] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[25] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[26] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[27] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[28] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[29] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[30] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[31] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2] -set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3] - -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_ck_p -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_ck_n -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[3] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[0] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[1] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[2] -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[3] - -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cas_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cke -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cs_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[0] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[1] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[2] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[3] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[4] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[5] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[6] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[7] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[8] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[9] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[10] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[11] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[12] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[13] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[14] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[15] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[16] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[17] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[18] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[19] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[20] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[21] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[22] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[23] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[24] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[25] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[26] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[27] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[28] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[29] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[30] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[31] -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_reset_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n -set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_rzq - -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[2] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[3] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[0] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[1] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[2] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[3] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[4] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[5] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[6] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[7] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[8] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[9] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[10] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[11] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[12] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[13] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[14] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[15] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[16] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[17] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[18] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[19] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[20] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[21] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[22] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[23] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[24] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[25] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[26] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[27] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[28] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[29] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[30] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[31] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3] -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_ck_p -set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_ck_n - -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[0] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[1] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[2] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[3] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[4] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[5] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[6] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[7] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[8] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[9] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[10] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[11] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[12] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[13] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_a[14] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[0] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[1] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ba[2] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cas_n -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ck_p -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ck_n -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cke -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_cs_n -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[0] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[1] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[2] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dm[3] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[0] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[1] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[2] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[3] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[4] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[5] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[6] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[7] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[8] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[9] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[10] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[11] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[12] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[13] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[14] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[15] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[16] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[17] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[18] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[19] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[20] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[21] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[22] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[23] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[24] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[25] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[26] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[27] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[28] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[29] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[30] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dq[31] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[0] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[1] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[2] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_p[3] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[0] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[1] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[2] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_dqs_n[3] -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_odt -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_ras_n -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_reset_n -set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_we_n - -set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst -set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to i_system_bd|sys_hps|hps_io|border|hps_sdram_inst|pll0|fbout - -set_location_assignment PIN_C28 -to ddr3_a[0] -set_location_assignment PIN_B28 -to ddr3_a[1] -set_location_assignment PIN_E26 -to ddr3_a[2] -set_location_assignment PIN_D26 -to ddr3_a[3] -set_location_assignment PIN_J21 -to ddr3_a[4] -set_location_assignment PIN_J20 -to ddr3_a[5] -set_location_assignment PIN_C26 -to ddr3_a[6] -set_location_assignment PIN_B26 -to ddr3_a[7] -set_location_assignment PIN_F26 -to ddr3_a[8] -set_location_assignment PIN_F25 -to ddr3_a[9] -set_location_assignment PIN_A24 -to ddr3_a[10] -set_location_assignment PIN_B24 -to ddr3_a[11] -set_location_assignment PIN_D24 -to ddr3_a[12] -set_location_assignment PIN_C24 -to ddr3_a[13] -set_location_assignment PIN_G23 -to ddr3_a[14] -set_location_assignment PIN_A27 -to ddr3_ba[0] -set_location_assignment PIN_H25 -to ddr3_ba[1] -set_location_assignment PIN_G25 -to ddr3_ba[2] -set_location_assignment PIN_V28 -to ddr3_reset_n -set_location_assignment PIN_N21 -to ddr3_ck_p -set_location_assignment PIN_N20 -to ddr3_ck_n -set_location_assignment PIN_L28 -to ddr3_cke -set_location_assignment PIN_L21 -to ddr3_cs_n -set_location_assignment PIN_A25 -to ddr3_ras_n -set_location_assignment PIN_A26 -to ddr3_cas_n -set_location_assignment PIN_E25 -to ddr3_we_n -set_location_assignment PIN_J25 -to ddr3_dq[0] -set_location_assignment PIN_J24 -to ddr3_dq[1] -set_location_assignment PIN_E28 -to ddr3_dq[2] -set_location_assignment PIN_D27 -to ddr3_dq[3] -set_location_assignment PIN_J26 -to ddr3_dq[4] -set_location_assignment PIN_K26 -to ddr3_dq[5] -set_location_assignment PIN_G27 -to ddr3_dq[6] -set_location_assignment PIN_F28 -to ddr3_dq[7] -set_location_assignment PIN_K25 -to ddr3_dq[8] -set_location_assignment PIN_L25 -to ddr3_dq[9] -set_location_assignment PIN_J27 -to ddr3_dq[10] -set_location_assignment PIN_J28 -to ddr3_dq[11] -set_location_assignment PIN_M27 -to ddr3_dq[12] -set_location_assignment PIN_M26 -to ddr3_dq[13] -set_location_assignment PIN_M28 -to ddr3_dq[14] -set_location_assignment PIN_N28 -to ddr3_dq[15] -set_location_assignment PIN_N24 -to ddr3_dq[16] -set_location_assignment PIN_N25 -to ddr3_dq[17] -set_location_assignment PIN_T28 -to ddr3_dq[18] -set_location_assignment PIN_U28 -to ddr3_dq[19] -set_location_assignment PIN_N26 -to ddr3_dq[20] -set_location_assignment PIN_N27 -to ddr3_dq[21] -set_location_assignment PIN_R27 -to ddr3_dq[22] -set_location_assignment PIN_V27 -to ddr3_dq[23] -set_location_assignment PIN_R26 -to ddr3_dq[24] -set_location_assignment PIN_R25 -to ddr3_dq[25] -set_location_assignment PIN_AA28 -to ddr3_dq[26] -set_location_assignment PIN_W26 -to ddr3_dq[27] -set_location_assignment PIN_R24 -to ddr3_dq[28] -set_location_assignment PIN_T24 -to ddr3_dq[29] -set_location_assignment PIN_Y27 -to ddr3_dq[30] -set_location_assignment PIN_AA27 -to ddr3_dq[31] -set_location_assignment PIN_R17 -to ddr3_dqs_p[0] -set_location_assignment PIN_R16 -to ddr3_dqs_n[0] -set_location_assignment PIN_R19 -to ddr3_dqs_p[1] -set_location_assignment PIN_R18 -to ddr3_dqs_n[1] -set_location_assignment PIN_T19 -to ddr3_dqs_p[2] -set_location_assignment PIN_T18 -to ddr3_dqs_n[2] -set_location_assignment PIN_U19 -to ddr3_dqs_p[3] -set_location_assignment PIN_T20 -to ddr3_dqs_n[3] -set_location_assignment PIN_G28 -to ddr3_dm[0] -set_location_assignment PIN_P28 -to ddr3_dm[1] -set_location_assignment PIN_W28 -to ddr3_dm[2] -set_location_assignment PIN_AB28 -to ddr3_dm[3] -set_location_assignment PIN_D28 -to ddr3_odt -set_location_assignment PIN_D25 -to ddr3_rzq - -execute_flow -compile - diff --git a/projects/de10/system_qsys.tcl b/projects/de10/system_qsys.tcl deleted file mode 100644 index f76d86087..000000000 --- a/projects/de10/system_qsys.tcl +++ /dev/null @@ -1,383 +0,0 @@ -# de10 generic qsys -# system clock - -add_instance sys_clk clock_source -set_instance_parameter_value sys_clk {clockFrequency} {50000000.0} -set_instance_parameter_value sys_clk {clockFrequencyKnown} {1} -set_instance_parameter_value sys_clk {resetSynchronousEdges} {NONE} -add_interface sys_clk clock sink -add_interface sys_rst reset sink -set_interface_property sys_clk EXPORT_OF sys_clk.clk_in -set_interface_property sys_rst EXPORT_OF sys_clk.clk_in_reset - -# hps - -variable hps_gpio_list -for {set i 0} {$i < 100} {incr i} { - lappend hps_gpio_list No -} - -proc set_hps_gpio_enable {gpio_index} { - - global hps_gpio_list - - regsub -all {[^0-9]} $gpio_index "" m_gpio_index - set hps_gpio_list [lreplace $hps_gpio_list $m_gpio_index $m_gpio_index Yes] -} - -set_hps_gpio_enable GPIO40 -set_hps_gpio_enable GPIO53 -set_hps_gpio_enable GPIO54 -set_hps_gpio_enable GPIO61 - -add_instance sys_hps altera_hps -set_instance_parameter_value sys_hps {MPU_EVENTS_Enable} {0} -set_instance_parameter_value sys_hps {F2SDRAM_Type} {} -set_instance_parameter_value sys_hps {F2SDRAM_Width} {} -set_instance_parameter_value sys_hps {F2SINTERRUPT_Enable} {1} -set_instance_parameter_value sys_hps {EMAC0_PinMuxing} {Unused} -set_instance_parameter_value sys_hps {EMAC0_Mode} {N/A} -set_instance_parameter_value sys_hps {EMAC1_PinMuxing} {HPS I/O Set 0} -set_instance_parameter_value sys_hps {EMAC1_Mode} {RGMII} -set_instance_parameter_value sys_hps {QSPI_PinMuxing} {HPS I/O Set 0} -set_instance_parameter_value sys_hps {QSPI_Mode} {1 SS} -set_instance_parameter_value sys_hps {SDIO_PinMuxing} {HPS I/O Set 0} -set_instance_parameter_value sys_hps {SDIO_Mode} {4-bit Data} -set_instance_parameter_value sys_hps {USB0_PinMuxing} {Unused} -set_instance_parameter_value sys_hps {USB0_Mode} {N/A} -set_instance_parameter_value sys_hps {USB1_PinMuxing} {HPS I/O Set 0} -set_instance_parameter_value sys_hps {USB1_Mode} {SDR} -set_instance_parameter_value sys_hps {SPIM0_PinMuxing} {FPGA} -set_instance_parameter_value sys_hps {SPIM0_Mode} {Full} -set_instance_parameter_value sys_hps {SPIM1_PinMuxing} {HPS I/O Set 0} -set_instance_parameter_value sys_hps {SPIM1_Mode} {Single Slave Select} -set_instance_parameter_value sys_hps {UART0_PinMuxing} {HPS I/O Set 0} -set_instance_parameter_value sys_hps {UART0_Mode} {No Flow Control} -set_instance_parameter_value sys_hps {UART1_PinMuxing} {Unused} -set_instance_parameter_value sys_hps {UART1_Mode} {N/A} -set_instance_parameter_value sys_hps {I2C0_PinMuxing} {HPS I/O Set 0} -set_instance_parameter_value sys_hps {I2C0_Mode} {I2C} -set_instance_parameter_value sys_hps {I2C1_PinMuxing} {HPS I/O Set 0} -set_instance_parameter_value sys_hps {I2C1_Mode} {I2C} -set_instance_parameter_value sys_hps {I2C2_PinMuxing} {FPGA} -set_instance_parameter_value sys_hps {I2C2_Mode} {Full} -set_instance_parameter_value sys_hps {I2C3_Mode} {Full} -set_instance_parameter_value sys_hps {I2C3_PinMuxing} {FPGA} -set_instance_parameter_value sys_hps {GPIO_Enable} $hps_gpio_list -set_instance_parameter_value sys_hps {desired_cfg_clk_mhz} {80.0} -set_instance_parameter_value sys_hps {S2FCLK_USER0CLK_Enable} {0} -set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_Enable} {0} -set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_Enable} {1} -set_instance_parameter_value sys_hps {S2FCLK_USER1CLK_FREQ} {100.0} -set_instance_parameter_value sys_hps {S2FCLK_USER2CLK_FREQ} {133.3} -set_instance_parameter_value sys_hps {HPS_PROTOCOL} {DDR3} -set_instance_parameter_value sys_hps {MEM_CLK_FREQ} {400.0} -set_instance_parameter_value sys_hps {REF_CLK_FREQ} {25.0} -set_instance_parameter_value sys_hps {MEM_VOLTAGE} {1.5V DDR3} -set_instance_parameter_value sys_hps {MEM_CLK_FREQ_MAX} {800.0} -set_instance_parameter_value sys_hps {MEM_DQ_WIDTH} {32} -set_instance_parameter_value sys_hps {MEM_ROW_ADDR_WIDTH} {15} -set_instance_parameter_value sys_hps {MEM_COL_ADDR_WIDTH} {10} -set_instance_parameter_value sys_hps {MEM_BANKADDR_WIDTH} {3} -set_instance_parameter_value sys_hps {MEM_TCL} {7} -set_instance_parameter_value sys_hps {MEM_DRV_STR} {RZQ/6} -set_instance_parameter_value sys_hps {MEM_RTT_NOM} {RZQ/6} -set_instance_parameter_value sys_hps {MEM_WTCL} {7} -set_instance_parameter_value sys_hps {MEM_RTT_WR} {Dynamic ODT off} -set_instance_parameter_value sys_hps {TIMING_TIS} {175} -set_instance_parameter_value sys_hps {TIMING_TIH} {250} -set_instance_parameter_value sys_hps {TIMING_TDS} {50} -set_instance_parameter_value sys_hps {TIMING_TDH} {125} -set_instance_parameter_value sys_hps {TIMING_TDQSQ} {120} -set_instance_parameter_value sys_hps {TIMING_TQH} {0.38} -set_instance_parameter_value sys_hps {TIMING_TDQSCK} {400} -set_instance_parameter_value sys_hps {TIMING_TDQSS} {0.25} -set_instance_parameter_value sys_hps {TIMING_TQSH} {0.38} -set_instance_parameter_value sys_hps {TIMING_TDSH} {0.2} -set_instance_parameter_value sys_hps {TIMING_TDSS} {0.2} -set_instance_parameter_value sys_hps {MEM_TINIT_US} {500} -set_instance_parameter_value sys_hps {MEM_TMRD_CK} {4} -set_instance_parameter_value sys_hps {MEM_TRAS_NS} {35.0} -set_instance_parameter_value sys_hps {MEM_TRCD_NS} {13.75} -set_instance_parameter_value sys_hps {MEM_TRP_NS} {13.75} -set_instance_parameter_value sys_hps {MEM_TREFI_US} {7.8} -set_instance_parameter_value sys_hps {MEM_TRFC_NS} {300.0} -set_instance_parameter_value sys_hps {MEM_TWR_NS} {15.0} -set_instance_parameter_value sys_hps {MEM_TWTR} {4} -set_instance_parameter_value sys_hps {MEM_TFAW_NS} {37.5} -set_instance_parameter_value sys_hps {MEM_TRRD_NS} {7.5} -set_instance_parameter_value sys_hps {MEM_TRTP_NS} {7.5} -set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_CK_DELAY} {0.6} -set_instance_parameter_value sys_hps {TIMING_BOARD_MAX_DQS_DELAY} {0.6} -set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MIN} {-0.01} -set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_CKDQS_DIMM_MAX} {0.01} -set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_WITHIN_DQS} {0.02} -set_instance_parameter_value sys_hps {TIMING_BOARD_SKEW_BETWEEN_DQS} {0.02} -set_instance_parameter_value sys_hps {TIMING_BOARD_DQ_TO_DQS_SKEW} {0.0} -set_instance_parameter_value sys_hps {TIMING_BOARD_AC_SKEW} {0.02} -set_instance_parameter_value sys_hps {TIMING_BOARD_AC_TO_CK_SKEW} {0.0} -add_interface sys_hps_memory conduit end -set_interface_property sys_hps_memory EXPORT_OF sys_hps.memory -add_interface sys_hps_hps_io conduit end -set_interface_property sys_hps_hps_io EXPORT_OF sys_hps.hps_io -add_interface sys_hps_h2f_reset reset source -set_interface_property sys_hps_h2f_reset EXPORT_OF sys_hps.h2f_reset -add_connection sys_clk.clk sys_hps.h2f_axi_clock -add_connection sys_clk.clk sys_hps.f2h_axi_clock -add_connection sys_clk.clk sys_hps.h2f_lw_axi_clock -add_interface sys_hps_i2c2 conduit end -set_interface_property sys_hps_i2c2 EXPORT_OF sys_hps.i2c2 -add_interface sys_hps_i2c2_clk clock source -set_interface_property sys_hps_i2c2_clk EXPORT_OF sys_hps.i2c2_clk -add_interface sys_hps_i2c2_scl_in clock sink -set_interface_property sys_hps_i2c2_scl_in EXPORT_OF sys_hps.i2c2_scl_in -add_interface sys_hps_spim0 conduit end -set_interface_property sys_hps_spim0 EXPORT_OF sys_hps.spim0 -add_interface sys_hps_spim0_clk clock source -set_interface_property sys_hps_spim0_clk EXPORT_OF sys_hps.spim0_sclk_out - -# cpu/hps handling - -proc ad_cpu_interrupt {m_irq m_port} { - - add_connection sys_hps.f2h_irq0 ${m_port} - set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq} -} - -proc ad_cpu_interconnect {m_base m_port} { - - add_connection sys_hps.h2f_lw_axi_master ${m_port} - set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base} -} - -# internal memory - -add_instance sys_int_mem altera_avalon_onchip_memory2 -set_instance_parameter_value sys_int_mem {dualPort} {0} -set_instance_parameter_value sys_int_mem {dataWidth} {64} -set_instance_parameter_value sys_int_mem {memorySize} {65536.0} -set_instance_parameter_value sys_int_mem {initMemContent} {0} -add_connection sys_clk.clk sys_int_mem.clk1 -add_connection sys_clk.clk_reset sys_int_mem.reset1 -add_connection sys_hps.h2f_axi_master sys_int_mem.s1 -set_connection_parameter_value sys_hps.h2f_axi_master/sys_int_mem.s1 baseAddress {0x0000} - -# id - -add_instance sys_id altera_avalon_sysid_qsys -set_instance_parameter_value sys_id {id} {-1395322110} -add_connection sys_clk.clk sys_id.clk -add_connection sys_clk.clk_reset sys_id.reset - -# gpio-bd - -add_instance sys_gpio_bd altera_avalon_pio -set_instance_parameter_value sys_gpio_bd {direction} {Bidir} -set_instance_parameter_value sys_gpio_bd {generateIRQ} {1} -set_instance_parameter_value sys_gpio_bd {width} {14} -add_connection sys_clk.clk sys_gpio_bd.clk -add_connection sys_clk.clk_reset sys_gpio_bd.reset -add_interface sys_gpio_bd conduit end -set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection - -# gpio-0 - -add_instance sys_gpio_0_0 altera_avalon_pio -set_instance_parameter_value sys_gpio_0_0 {direction} {Bidir} -set_instance_parameter_value sys_gpio_0_0 {generateIRQ} {1} -set_instance_parameter_value sys_gpio_0_0 {width} {32} -add_connection sys_clk.clk sys_gpio_0_0.clk -add_connection sys_clk.clk_reset sys_gpio_0_0.reset -add_interface sys_gpio_0_0 conduit end -set_interface_property sys_gpio_0_0 EXPORT_OF sys_gpio_0_0.external_connection - -add_instance sys_gpio_0_1 altera_avalon_pio -set_instance_parameter_value sys_gpio_0_1 {direction} {Bidir} -set_instance_parameter_value sys_gpio_0_1 {generateIRQ} {1} -set_instance_parameter_value sys_gpio_0_1 {width} {4} -add_connection sys_clk.clk sys_gpio_0_1.clk -add_connection sys_clk.clk_reset sys_gpio_0_1.reset -add_interface sys_gpio_0_1 conduit end -set_interface_property sys_gpio_0_1 EXPORT_OF sys_gpio_0_1.external_connection - -# gpio-1 - -add_instance sys_gpio_1_0 altera_avalon_pio -set_instance_parameter_value sys_gpio_1_0 {direction} {Bidir} -set_instance_parameter_value sys_gpio_1_0 {generateIRQ} {1} -set_instance_parameter_value sys_gpio_1_0 {width} {32} -add_connection sys_clk.clk_reset sys_gpio_1_0.reset -add_connection sys_clk.clk sys_gpio_1_0.clk -add_interface sys_gpio_1_0 conduit end -set_interface_property sys_gpio_1_0 EXPORT_OF sys_gpio_1_0.external_connection - -add_instance sys_gpio_1_1 altera_avalon_pio -set_instance_parameter_value sys_gpio_1_1 {direction} {Bidir} -set_instance_parameter_value sys_gpio_1_1 {generateIRQ} {1} -set_instance_parameter_value sys_gpio_1_1 {width} {4} -add_connection sys_clk.clk_reset sys_gpio_1_1.reset -add_connection sys_clk.clk sys_gpio_1_1.clk -add_interface sys_gpio_1_1 conduit end -set_interface_property sys_gpio_1_1 EXPORT_OF sys_gpio_1_1.external_connection - -# gpio-arduino - -add_instance sys_gpio_arduino altera_avalon_pio -set_instance_parameter_value sys_gpio_arduino {direction} {Bidir} -set_instance_parameter_value sys_gpio_arduino {generateIRQ} {1} -set_instance_parameter_value sys_gpio_arduino {width} {8} -add_connection sys_clk.clk sys_gpio_arduino.clk -add_connection sys_clk.clk_reset sys_gpio_arduino.reset -add_interface sys_gpio_arduino conduit end -set_interface_property sys_gpio_arduino EXPORT_OF sys_gpio_arduino.external_connection - -# HDMI - -add_instance axi_hdmi_tx_0 axi_hdmi_tx 1.0 -set_instance_parameter_value axi_hdmi_tx_0 {CR_CB_N} {0} -set_instance_parameter_value axi_hdmi_tx_0 {DEVICE_TYPE} {16} -set_instance_parameter_value axi_hdmi_tx_0 {EMBEDDED_SYNC} {0} -set_instance_parameter_value axi_hdmi_tx_0 {ID} {0} - -add_instance pixel_clk_pll altera_pll 17.1 -set_instance_parameter_value pixel_clk_pll {gui_operation_mode} {direct} -set_instance_parameter_value pixel_clk_pll {gui_output_clock_frequency0} {108.0} -set_instance_parameter_value pixel_clk_pll {gui_phase_shift0} {0} -set_instance_parameter_value pixel_clk_pll {gui_phase_shift_deg0} {0.0} -set_instance_parameter_value pixel_clk_pll {gui_phout_division} {1} -set_instance_parameter_value pixel_clk_pll {gui_pll_auto_reset} {Off} -set_instance_parameter_value pixel_clk_pll {gui_pll_bandwidth_preset} {Auto} -set_instance_parameter_value pixel_clk_pll {gui_pll_cascading_mode} {Create an adjpllin signal to connect with an upstream PLL} -set_instance_parameter_value pixel_clk_pll {gui_pll_mode} {Integer-N PLL} -set_instance_parameter_value pixel_clk_pll {gui_ps_units0} {ps} -set_instance_parameter_value pixel_clk_pll {gui_refclk1_frequency} {100.0} -set_instance_parameter_value pixel_clk_pll {gui_refclk_switch} {0} -set_instance_parameter_value pixel_clk_pll {gui_reference_clock_frequency} {50.0} -set_instance_parameter_value pixel_clk_pll {gui_switchover_delay} {0} -set_instance_parameter_value pixel_clk_pll {gui_en_reconf} {1} - -add_instance pixel_clk_pll_reconfig altera_pll_reconfig 17.1 -set_instance_parameter_value pixel_clk_pll_reconfig {ENABLE_BYTEENABLE} {0} -set_instance_parameter_value pixel_clk_pll_reconfig {ENABLE_MIF} {0} -set_instance_parameter_value pixel_clk_pll_reconfig {MIF_FILE_NAME} {} - -add_instance video_dmac axi_dmac 1.0 -set_instance_parameter_value video_dmac {ASYNC_CLK_DEST_REQ_MANUAL} {1} -set_instance_parameter_value video_dmac {ASYNC_CLK_REQ_SRC_MANUAL} {1} -set_instance_parameter_value video_dmac {ASYNC_CLK_SRC_DEST_MANUAL} {1} -set_instance_parameter_value video_dmac {AUTO_ASYNC_CLK} {1} -set_instance_parameter_value video_dmac {AXI_SLICE_DEST} {0} -set_instance_parameter_value video_dmac {AXI_SLICE_SRC} {0} -set_instance_parameter_value video_dmac {CYCLIC} {1} -set_instance_parameter_value video_dmac {DMA_2D_TRANSFER} {1} -set_instance_parameter_value video_dmac {DMA_DATA_WIDTH_DEST} {64} -set_instance_parameter_value video_dmac {DMA_DATA_WIDTH_SRC} {64} -set_instance_parameter_value video_dmac {DMA_LENGTH_WIDTH} {24} -set_instance_parameter_value video_dmac {DMA_TYPE_DEST} {1} -set_instance_parameter_value video_dmac {DMA_TYPE_SRC} {0} -set_instance_parameter_value video_dmac {FIFO_SIZE} {4} -set_instance_parameter_value video_dmac {ID} {0} -set_instance_parameter_value video_dmac {SYNC_TRANSFER_START} {0} - -add_interface axi_dmac_0_if_m_axis_data conduit end -set_interface_property axi_dmac_0_if_m_axis_data EXPORT_OF video_dmac.if_m_axis_data -add_interface axi_dmac_0_if_m_axis_ready conduit end -set_interface_property axi_dmac_0_if_m_axis_ready EXPORT_OF video_dmac.if_m_axis_ready -add_interface axi_dmac_0_if_m_axis_valid conduit end -set_interface_property axi_dmac_0_if_m_axis_valid EXPORT_OF video_dmac.if_m_axis_valid -add_interface axi_hdmi_tx_0_hdmi_if conduit end -set_interface_property axi_hdmi_tx_0_hdmi_if EXPORT_OF axi_hdmi_tx_0.hdmi_if -add_interface axi_hdmi_tx_0_if_vdma_fs conduit end -set_interface_property axi_hdmi_tx_0_if_vdma_fs EXPORT_OF axi_hdmi_tx_0.if_vdma_fs -add_interface axi_hdmi_tx_0_if_vdma_fs_ret conduit end -set_interface_property axi_hdmi_tx_0_if_vdma_fs_ret EXPORT_OF axi_hdmi_tx_0.if_vdma_fs_ret -add_interface axi_hdmi_tx_0_vdma_if avalon_streaming sink -set_interface_property axi_hdmi_tx_0_vdma_if EXPORT_OF axi_hdmi_tx_0.vdma_if - -add_connection pixel_clk_pll.outclk0 axi_hdmi_tx_0.hdmi_clock - -add_connection pixel_clk_pll.reconfig_from_pll pixel_clk_pll_reconfig.reconfig_from_pll -set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll endPort {} -set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll endPortLSB {0} -set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll startPort {} -set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll startPortLSB {0} -set_connection_parameter_value pixel_clk_pll.reconfig_from_pll/pixel_clk_pll_reconfig.reconfig_from_pll width {0} - -add_connection pixel_clk_pll.reconfig_to_pll pixel_clk_pll_reconfig.reconfig_to_pll -set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll endPort {} -set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll endPortLSB {0} -set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll startPort {} -set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll startPortLSB {0} -set_connection_parameter_value pixel_clk_pll.reconfig_to_pll/pixel_clk_pll_reconfig.reconfig_to_pll width {0} - -add_connection sys_clk.clk axi_hdmi_tx_0.s_axi_clock - -add_connection sys_clk.clk pixel_clk_pll.refclk - -add_connection sys_clk.clk pixel_clk_pll_reconfig.mgmt_clk - -add_connection sys_clk.clk video_dmac.s_axi_clock - -add_connection sys_clk.clk_reset axi_hdmi_tx_0.s_axi_reset - -add_connection sys_clk.clk_reset pixel_clk_pll.reset - -add_connection sys_clk.clk_reset pixel_clk_pll_reconfig.mgmt_reset - -add_connection sys_clk.clk_reset video_dmac.m_src_axi_reset - -add_connection sys_clk.clk_reset video_dmac.s_axi_reset - -add_connection sys_hps.h2f_user2_clock axi_hdmi_tx_0.vdma_clock - -add_connection sys_hps.h2f_user2_clock sys_hps.f2h_axi_clock - -add_connection sys_hps.h2f_user2_clock video_dmac.if_m_axis_aclk - -add_connection sys_hps.h2f_user2_clock video_dmac.m_src_axi_clock - -add_connection video_dmac.m_src_axi sys_hps.f2h_axi_slave -set_connection_parameter_value video_dmac.m_src_axi/sys_hps.f2h_axi_slave arbitrationPriority {1} -set_connection_parameter_value video_dmac.m_src_axi/sys_hps.f2h_axi_slave baseAddress {0x0000} -set_connection_parameter_value video_dmac.m_src_axi/sys_hps.f2h_axi_slave defaultConnection {0} - -add_interface sys_hps_i2c3 conduit end -set_interface_property sys_hps_i2c3 EXPORT_OF sys_hps.i2c3 -add_interface sys_hps_i2c3_clk clock source -set_interface_property sys_hps_i2c3_clk EXPORT_OF sys_hps.i2c3_clk -add_interface sys_hps_i2c3_scl_in clock sink -set_interface_property sys_hps_i2c3_scl_in EXPORT_OF sys_hps.i2c3_scl_in - -# io-interrupts - -add_instance sys_hps_irq altera_irq_bridge -set_instance_parameter_value sys_hps_irq {IRQ_N} {0} -set_instance_parameter_value sys_hps_irq {IRQ_WIDTH} {1} -add_connection sys_clk.clk sys_hps_irq.clk -add_connection sys_clk.clk_reset sys_hps_irq.clk_reset -add_interface sys_hps_irq_in interrupt receiver -set_interface_property sys_hps_irq_in EXPORT_OF sys_hps_irq.receiver_irq - -# interrupts - -ad_cpu_interrupt 0 sys_gpio_bd.irq -ad_cpu_interrupt 1 sys_gpio_0_0.irq -ad_cpu_interrupt 2 sys_gpio_0_1.irq -ad_cpu_interrupt 3 sys_gpio_1_0.irq -ad_cpu_interrupt 4 sys_gpio_1_1.irq -ad_cpu_interrupt 5 sys_gpio_arduino.irq -ad_cpu_interrupt 6 sys_hps_irq.sender0_irq -ad_cpu_interrupt 7 video_dmac.interrupt_sender - -# cpu interconnects - -ad_cpu_interconnect 0x00010000 sys_id.control_slave -ad_cpu_interconnect 0x00010080 sys_gpio_bd.s1 -ad_cpu_interconnect 0x00010100 sys_gpio_0_0.s1 -ad_cpu_interconnect 0x00010200 sys_gpio_0_1.s1 -ad_cpu_interconnect 0x00010300 sys_gpio_1_0.s1 -ad_cpu_interconnect 0x00010400 sys_gpio_1_1.s1 -ad_cpu_interconnect 0x00010500 sys_gpio_arduino.s1 -ad_cpu_interconnect 0x00080000 video_dmac.s_axi -ad_cpu_interconnect 0x00090000 axi_hdmi_tx_0.s_axi - diff --git a/projects/de10/system_top.v b/projects/de10/system_top.v deleted file mode 100644 index e61e5897e..000000000 --- a/projects/de10/system_top.v +++ /dev/null @@ -1,314 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - // clock and resets - - input sys_clk, - - // hps-ddr - - output [ 14:0] ddr3_a, - output [ 2:0] ddr3_ba, - output ddr3_reset_n, - output ddr3_ck_p, - output ddr3_ck_n, - output ddr3_cke, - output ddr3_cs_n, - output ddr3_ras_n, - output ddr3_cas_n, - output ddr3_we_n, - inout [ 31:0] ddr3_dq, - inout [ 3:0] ddr3_dqs_p, - inout [ 3:0] ddr3_dqs_n, - output [ 3:0] ddr3_dm, - output ddr3_odt, - input ddr3_rzq, - - // hps-ethernet - - output eth1_tx_clk, - output eth1_tx_ctl, - output [ 3:0] eth1_tx_d, - input eth1_rx_clk, - input eth1_rx_ctl, - input [ 3:0] eth1_rx_d, - output eth1_mdc, - inout eth1_mdio, - - // hps-qspi - - output qspi_ss0, - output qspi_clk, - inout [ 3:0] qspi_io, - - // hps-sdio - - output sdio_clk, - inout sdio_cmd, - inout [ 3:0] sdio_d, - - // hps-usb - - input usb1_clk, - output usb1_stp, - input usb1_dir, - input usb1_nxt, - inout [ 7:0] usb1_d, - - // hps-uart - - input uart0_rx, - output uart0_tx, - - // board gpio - - inout [ 35:0] gpio_0, - inout [ 35:0] gpio_1, - inout [ 13:0] gpio_bd, - inout hps_gpio_led, - inout hps_gpio_pb, - - // adxl345 iic interface - - inout adxl345_scl, - inout adxl345_sda, - inout adxl345_int, - - // ltc connector iic/spi interface - - inout ltc_i2c_spi_sel, - inout ltc_i2c_scl, - inout ltc_i2c_sda, - output ltc_spi_csn, - output ltc_spi_clk, - output ltc_spi_mosi, - input ltc_spi_miso, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [ 23:0] hdmi_data, - - inout hdmi_i2c_scl, - inout hdmi_i2c_sda, - inout hdmi_i2s, - inout hdmi_lrclk, - inout hdmi_mclk, - inout hdmi_sclk, - - // arduino interface - - inout arduino_i2c_scl, - inout arduino_i2c_sda, - output [ 3:0] arduino_spi_csn, - output arduino_spi_clk, - output arduino_spi_mosi, - input arduino_spi_miso, - inout arduino_reset_n, - inout [ 6:0] arduino_gpio); - - // internal signals - - wire sys_resetn; - wire i2c2_scl_oe; - wire i2c2_scl; - wire i2c2_sda_oe; - wire i2c2_sda; - - wire i2c3_scl_oe; - wire i2c3_scl; - wire i2c3_sda_oe; - wire i2c3_sda; - - wire hdmi_valid_s; - wire hdmi_ready_s; - wire [ 63:0] hdmi_data_s; - wire hdmi_fs; - - // instantiations - - ALT_IOBUF iobuf_i2c2_scl ( - .i (1'b0), - .oe (i2c2_scl_oe), - .o (i2c2_scl), - .io (arduino_i2c_scl)); - - ALT_IOBUF iobuf_i2c2_sda ( - .i (1'b0), - .oe (i2c2_sda_oe), - .o (i2c2_sda), - .io (arduino_i2c_sda)); - - ALT_IOBUF iobuf_i2c3_scl ( - .i (1'b0), - .oe (i2c3_scl_oe), - .o (i2c3_scl), - .io (hdmi_i2c_scl)); - - ALT_IOBUF iobuf_i2c3_sda ( - .i (1'b0), - .oe (i2c3_sda_oe), - .o (i2c3_sda), - .io (hdmi_i2c_sda)); - - system_bd i_system_bd ( - .sys_clk_clk (sys_clk), - .sys_gpio_0_0_export (gpio_0[31:0]), - .sys_gpio_0_1_export (gpio_0[35:32]), - .sys_gpio_1_0_export (gpio_1[31:0]), - .sys_gpio_1_1_export (gpio_1[35:32]), - .sys_gpio_arduino_export ({arduino_reset_n, arduino_gpio}), - .sys_gpio_bd_export (gpio_bd), - .sys_hps_h2f_reset_reset_n (sys_resetn), - .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk), - .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]), - .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]), - .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]), - .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]), - .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]), - .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio), - .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc), - .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl), - .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl), - .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk), - .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]), - .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]), - .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]), - .sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io[0]), - .sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io[1]), - .sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io[2]), - .sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io[3]), - .sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0), - .sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk), - .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd), - .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]), - .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]), - .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk), - .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]), - .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]), - .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]), - .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]), - .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]), - .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]), - .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]), - .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]), - .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]), - .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]), - .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk), - .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp), - .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir), - .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt), - .sys_hps_hps_io_hps_io_spim1_inst_CLK (ltc_spi_clk), - .sys_hps_hps_io_hps_io_spim1_inst_MOSI (ltc_spi_mosi), - .sys_hps_hps_io_hps_io_spim1_inst_MISO (ltc_spi_miso), - .sys_hps_hps_io_hps_io_spim1_inst_SS0 (ltc_spi_csn), - .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx), - .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx), - .sys_hps_hps_io_hps_io_i2c0_inst_SDA (adxl345_sda), - .sys_hps_hps_io_hps_io_i2c0_inst_SCL (adxl345_scl), - .sys_hps_hps_io_hps_io_i2c1_inst_SDA (ltc_i2c_sda), - .sys_hps_hps_io_hps_io_i2c1_inst_SCL (ltc_i2c_scl), - .sys_hps_hps_io_hps_io_gpio_inst_GPIO40 (ltc_i2c_spi_sel), - .sys_hps_hps_io_hps_io_gpio_inst_GPIO53 (hps_gpio_led), - .sys_hps_hps_io_hps_io_gpio_inst_GPIO54 (hps_gpio_pb), - .sys_hps_hps_io_hps_io_gpio_inst_GPIO61 (adxl345_int), - .sys_hps_i2c2_out_data(i2c2_sda_oe), - .sys_hps_i2c2_sda(i2c2_sda), - .sys_hps_i2c2_clk_clk(i2c2_scl_oe), - .sys_hps_i2c2_scl_in_clk(i2c2_scl), - .sys_hps_irq_in_irq (1'd0), - .sys_hps_memory_mem_a (ddr3_a), - .sys_hps_memory_mem_ba (ddr3_ba), - .sys_hps_memory_mem_ck (ddr3_ck_p), - .sys_hps_memory_mem_ck_n (ddr3_ck_n), - .sys_hps_memory_mem_cke (ddr3_cke), - .sys_hps_memory_mem_cs_n (ddr3_cs_n), - .sys_hps_memory_mem_ras_n (ddr3_ras_n), - .sys_hps_memory_mem_cas_n (ddr3_cas_n), - .sys_hps_memory_mem_we_n (ddr3_we_n), - .sys_hps_memory_mem_reset_n (ddr3_reset_n), - .sys_hps_memory_mem_dq (ddr3_dq), - .sys_hps_memory_mem_dqs (ddr3_dqs_p), - .sys_hps_memory_mem_dqs_n (ddr3_dqs_n), - .sys_hps_memory_mem_odt (ddr3_odt), - .sys_hps_memory_mem_dm (ddr3_dm), - .sys_hps_memory_oct_rzqin (ddr3_rzq), - .sys_hps_spim0_txd (arduino_spi_mosi), - .sys_hps_spim0_rxd (arduino_spi_miso), - .sys_hps_spim0_ss_in_n (1'b1), - .sys_hps_spim0_ssi_oe_n (), - .sys_hps_spim0_ss_0_n (arduino_spi_csn[0]), - .sys_hps_spim0_ss_1_n (arduino_spi_csn[1]), - .sys_hps_spim0_ss_2_n (arduino_spi_csn[2]), - .sys_hps_spim0_ss_3_n (arduino_spi_csn[3]), - .sys_hps_spim0_clk_clk (arduino_spi_clk), - .axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk), - .axi_hdmi_tx_0_hdmi_if_h16_hsync (), - .axi_hdmi_tx_0_hdmi_if_h16_vsync (), - .axi_hdmi_tx_0_hdmi_if_h16_data_e (), - .axi_hdmi_tx_0_hdmi_if_h16_data (), - .axi_hdmi_tx_0_hdmi_if_h16_es_data (), - .axi_hdmi_tx_0_hdmi_if_h24_hsync (hdmi_hsync), - .axi_hdmi_tx_0_hdmi_if_h24_vsync (hdmi_vsync), - .axi_hdmi_tx_0_hdmi_if_h24_data_e (hdmi_data_e), - .axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data), - .axi_hdmi_tx_0_hdmi_if_h36_hsync (), - .axi_hdmi_tx_0_hdmi_if_h36_vsync (), - .axi_hdmi_tx_0_hdmi_if_h36_data_e (), - .axi_hdmi_tx_0_hdmi_if_h36_data (), - .axi_hdmi_tx_0_vdma_if_valid (hdmi_valid_s), - .axi_hdmi_tx_0_vdma_if_data (hdmi_data_s), - .axi_hdmi_tx_0_vdma_if_ready (hdmi_ready_s), - .axi_hdmi_tx_0_if_vdma_fs_vdma_fs (hdmi_fs), - .axi_hdmi_tx_0_if_vdma_fs_ret_vdma_fs_ret (hdmi_fs), - .axi_dmac_0_if_m_axis_valid_valid (hdmi_valid_s), - .axi_dmac_0_if_m_axis_data_data (hdmi_data_s), - .axi_dmac_0_if_m_axis_ready_ready (hdmi_ready_s), - .sys_hps_i2c3_scl_in_clk (i2c3_scl), - .sys_hps_i2c3_clk_clk (i2c3_scl_oe), - .sys_hps_i2c3_out_data (i2c3_sda_oe), - .sys_hps_i2c3_sda (i2c3_sda), - .sys_rst_reset_n (sys_resetn) - ); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/fmcomms2/ac701/Makefile b/projects/fmcomms2/ac701/Makefile deleted file mode 100644 index cf5d93de4..000000000 --- a/projects/fmcomms2/ac701/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := fmcomms2_ac701 - -M_DEPS += ../common/fmcomms2_bd.tcl -M_DEPS += ../../common/ac701/ac701_system_mig.prj -M_DEPS += ../../common/ac701/ac701_system_constr.xdc -M_DEPS += ../../common/ac701/ac701_system_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v -M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl - -LIB_DEPS += axi_ad9361 -LIB_DEPS += axi_dmac -LIB_DEPS += util_clkdiv -LIB_DEPS += util_cpack -LIB_DEPS += util_rfifo -LIB_DEPS += util_tdd_sync -LIB_DEPS += util_upack -LIB_DEPS += util_wfifo - -include ../../scripts/project-xilinx.mk diff --git a/projects/fmcomms2/ac701/system_bd.tcl b/projects/fmcomms2/ac701/system_bd.tcl deleted file mode 100644 index 1edd0a655..000000000 --- a/projects/fmcomms2/ac701/system_bd.tcl +++ /dev/null @@ -1,6 +0,0 @@ - -source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl -source ../common/fmcomms2_bd.tcl - -ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 25 - diff --git a/projects/fmcomms2/ac701/system_constr.xdc b/projects/fmcomms2/ac701/system_constr.xdc deleted file mode 100644 index 4a50da3eb..000000000 --- a/projects/fmcomms2/ac701/system_constr.xdc +++ /dev/null @@ -1,65 +0,0 @@ - -# constraints -# ad9361 - -set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N - -set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N -set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N -set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P -set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N -set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N -set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P -set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N -set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P - -set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N - -set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn_0] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N - -# clocks - -create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p] - diff --git a/projects/fmcomms2/ac701/system_project.tcl b/projects/fmcomms2/ac701/system_project.tcl deleted file mode 100644 index af93bb163..000000000 --- a/projects/fmcomms2/ac701/system_project.tcl +++ /dev/null @@ -1,15 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_xilinx fmcomms2_ac701 -adi_project_files fmcomms2_ac701 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ] - -adi_project_run fmcomms2_ac701 -source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl - diff --git a/projects/fmcomms2/ac701/system_top.v b/projects/fmcomms2/ac701/system_top.v deleted file mode 100644 index b2ab0a14a..000000000 --- a/projects/fmcomms2/ac701/system_top.v +++ /dev/null @@ -1,215 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - input sys_rst, - input sys_clk_p, - input sys_clk_n, - - input uart_sin, - output uart_sout, - - output [13:0] ddr3_addr, - output [ 2:0] ddr3_ba, - output ddr3_cas_n, - output [ 0:0] ddr3_ck_n, - output [ 0:0] ddr3_ck_p, - output [ 0:0] ddr3_cke, - output [ 0:0] ddr3_cs_n, - output [ 7:0] ddr3_dm, - inout [63:0] ddr3_dq, - inout [ 7:0] ddr3_dqs_n, - inout [ 7:0] ddr3_dqs_p, - output [ 0:0] ddr3_odt, - output ddr3_ras_n, - output ddr3_reset_n, - output ddr3_we_n, - - output phy_reset_n, - output phy_mdc, - inout phy_mdio, - output phy_tx_clk, - output phy_tx_ctrl, - output [ 3:0] phy_tx_data, - input phy_rx_clk, - input phy_rx_ctrl, - input [ 3:0] phy_rx_data, - - output fan_pwm, - - inout [ 6:0] gpio_lcd, - inout [12:0] gpio_bd, - - output iic_rstn, - inout iic_scl, - inout iic_sda, - - input rx_clk_in_p, - input rx_clk_in_n, - input rx_frame_in_p, - input rx_frame_in_n, - input [ 5:0] rx_data_in_p, - input [ 5:0] rx_data_in_n, - - output tx_clk_out_p, - output tx_clk_out_n, - output tx_frame_out_p, - output tx_frame_out_n, - output [ 5:0] tx_data_out_p, - output [ 5:0] tx_data_out_n, - - output txnrx, - output enable, - - inout gpio_resetb, - inout gpio_sync, - inout gpio_en_agc, - inout [ 3:0] gpio_ctl, - inout [ 7:0] gpio_status, - - output spi_csn_0, - output spi_clk, - output spi_mosi, - input spi_miso ); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [ 7:0] spi_csn; - wire spi_clk; - wire spi_mosi; - wire spi_miso; - - // assignments - - assign fan_pwm = 1'b1; - assign iic_rstn = 1'b1; - assign spi_csn_0 = spi_csn[0]; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(15)) i_iobuf ( - .dio_t (gpio_t[46:32]), - .dio_i (gpio_o[46:32]), - .dio_o (gpio_i[46:32]), - .dio_p ({ gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status})); - - ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_sw_led ( - .dio_t (gpio_t[12:0]), - .dio_i (gpio_o[12:0]), - .dio_o (gpio_i[12:0]), - .dio_p (gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr3_addr (ddr3_addr), - .ddr3_ba (ddr3_ba), - .ddr3_cas_n (ddr3_cas_n), - .ddr3_ck_n (ddr3_ck_n), - .ddr3_ck_p (ddr3_ck_p), - .ddr3_cke (ddr3_cke), - .ddr3_cs_n (ddr3_cs_n), - .ddr3_dm (ddr3_dm), - .ddr3_dq (ddr3_dq), - .ddr3_dqs_n (ddr3_dqs_n), - .ddr3_dqs_p (ddr3_dqs_p), - .ddr3_odt (ddr3_odt), - .ddr3_ras_n (ddr3_ras_n), - .ddr3_reset_n (ddr3_reset_n), - .ddr3_we_n (ddr3_we_n), - .gpio_lcd_tri_io (gpio_lcd), - .gpio0_o (gpio_o[31:0]), - .gpio0_t (gpio_t[31:0]), - .gpio0_i (gpio_i[31:0]), - .gpio1_o (gpio_o[63:32]), - .gpio1_t (gpio_t[63:32]), - .gpio1_i (gpio_i[63:32]), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .mb_intr_06 (1'b0), - .mb_intr_07 (1'b0), - .mb_intr_08 (1'b0), - .mb_intr_14 (1'b0), - .mb_intr_15 (1'b0), - .mdio_mdio_io (phy_mdio), - .mdio_mdc (phy_mdc), - .phy_rst_n (phy_reset_n), - .rgmii_rd (phy_rx_data), - .rgmii_rx_ctl (phy_rx_ctrl), - .rgmii_rxc (phy_rx_clk), - .rgmii_td (phy_tx_data), - .rgmii_tx_ctl (phy_tx_ctrl), - .rgmii_txc (phy_tx_clk), - .sys_clk_n (sys_clk_n), - .sys_clk_p (sys_clk_p), - .sys_rst (sys_rst), - .spi_clk_i (spi_clk), - .spi_clk_o (spi_clk), - .spi_csn_i (spi_csn), - .spi_csn_o (spi_csn), - .spi_sdi_i (spi_miso), - .spi_sdo_i (spi_mosi), - .spi_sdo_o (spi_mosi), - .rx_clk_in_n (rx_clk_in_n), - .rx_clk_in_p (rx_clk_in_p), - .rx_data_in_n (rx_data_in_n), - .rx_data_in_p (rx_data_in_p), - .rx_frame_in_n (rx_frame_in_n), - .rx_frame_in_p (rx_frame_in_p), - .tx_clk_out_n (tx_clk_out_n), - .tx_clk_out_p (tx_clk_out_p), - .tx_data_out_n (tx_data_out_n), - .tx_data_out_p (tx_data_out_p), - .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p), - .uart_sin (uart_sin), - .uart_sout (uart_sout), - .enable (enable), - .txnrx (txnrx), - .up_enable (gpio_o[47]), - .up_txnrx (gpio_o[48])); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/fmcomms2/mitx045/Makefile b/projects/fmcomms2/mitx045/Makefile deleted file mode 100644 index 81a7aeb18..000000000 --- a/projects/fmcomms2/mitx045/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := fmcomms2_mitx045 - -M_DEPS += ../common/fmcomms2_bd.tcl -M_DEPS += ../../common/mitx045/mitx045_system_ps7.tcl -M_DEPS += ../../common/mitx045/mitx045_system_constr.xdc -M_DEPS += ../../common/mitx045/mitx045_system_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v -M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl - -LIB_DEPS += axi_ad9361 -LIB_DEPS += axi_clkgen -LIB_DEPS += axi_dmac -LIB_DEPS += axi_hdmi_tx -LIB_DEPS += axi_i2s_adi -LIB_DEPS += axi_spdif_tx -LIB_DEPS += util_clkdiv -LIB_DEPS += util_cpack -LIB_DEPS += util_rfifo -LIB_DEPS += util_tdd_sync -LIB_DEPS += util_upack -LIB_DEPS += util_wfifo - -include ../../scripts/project-xilinx.mk diff --git a/projects/fmcomms2/mitx045/system_bd.tcl b/projects/fmcomms2/mitx045/system_bd.tcl deleted file mode 100644 index 3f0586c10..000000000 --- a/projects/fmcomms2/mitx045/system_bd.tcl +++ /dev/null @@ -1,6 +0,0 @@ - -source $ad_hdl_dir/projects/common/mitx045/mitx045_system_bd.tcl -source ../common/fmcomms2_bd.tcl - -ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 20 - diff --git a/projects/fmcomms2/mitx045/system_constr.xdc b/projects/fmcomms2/mitx045/system_constr.xdc deleted file mode 100644 index 403bbc60f..000000000 --- a/projects/fmcomms2/mitx045/system_constr.xdc +++ /dev/null @@ -1,64 +0,0 @@ - -# constraints -# ad9361 - -set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P -set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N -set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P -set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N -set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N - -set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P -set_property -dict {PACKAGE_PIN AK12 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N -set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P -set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N -set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P -set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N -set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P -set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N -set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N -set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P -set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N -set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N - -set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N - -# clocks - -create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p] - diff --git a/projects/fmcomms2/mitx045/system_project.tcl b/projects/fmcomms2/mitx045/system_project.tcl deleted file mode 100644 index ad6829409..000000000 --- a/projects/fmcomms2/mitx045/system_project.tcl +++ /dev/null @@ -1,15 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_xilinx fmcomms2_mitx045 -adi_project_files fmcomms2_mitx045 [list \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/mitx045/mitx045_system_constr.xdc" ] - -adi_project_run fmcomms2_mitx045 -source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl - diff --git a/projects/fmcomms2/mitx045/system_top.v b/projects/fmcomms2/mitx045/system_top.v deleted file mode 100644 index 9237a9494..000000000 --- a/projects/fmcomms2/mitx045/system_top.v +++ /dev/null @@ -1,221 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [11:0] gpio_bd, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [15:0] hdmi_data, - - output spdif, - - output i2s_mclk, - output i2s_bclk, - output i2s_lrclk, - output i2s_sdata_out, - input i2s_sdata_in, - - inout iic_scl, - inout iic_sda, - - input rx_clk_in_p, - input rx_clk_in_n, - input rx_frame_in_p, - input rx_frame_in_n, - input [ 5:0] rx_data_in_p, - input [ 5:0] rx_data_in_n, - output tx_clk_out_p, - output tx_clk_out_n, - output tx_frame_out_p, - output tx_frame_out_n, - output [ 5:0] tx_data_out_p, - output [ 5:0] tx_data_out_n, - - output txnrx, - output enable, - - inout gpio_resetb, - inout gpio_sync, - inout gpio_en_agc, - inout [ 3:0] gpio_ctl, - inout [ 7:0] gpio_status, - - output spi_csn, - output spi_clk, - output spi_mosi, - input spi_miso); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(15)) i_iobuf ( - .dio_t (gpio_t[46:32]), - .dio_i (gpio_o[46:32]), - .dio_o (gpio_i[46:32]), - .dio_p ({ gpio_resetb, - gpio_sync, - gpio_en_agc, - gpio_ctl, - gpio_status})); - - ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_bd ( - .dio_t (gpio_t[11:0]), - .dio_i (gpio_o[11:0]), - .dio_o (gpio_i[11:0]), - .dio_p (gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .i2s_bclk (i2s_bclk), - .i2s_lrclk (i2s_lrclk), - .i2s_mclk (i2s_mclk), - .i2s_sdata_in (i2s_sdata_in), - .i2s_sdata_out (i2s_sdata_out), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_10 (1'b0), - .ps_intr_11 (1'b0), - .rx_clk_in_n (rx_clk_in_n), - .rx_clk_in_p (rx_clk_in_p), - .rx_data_in_n (rx_data_in_n), - .rx_data_in_p (rx_data_in_p), - .rx_frame_in_n (rx_frame_in_n), - .rx_frame_in_p (rx_frame_in_p), - .spdif (spdif), - .spi0_clk_i (1'b0), - .spi0_clk_o (spi_clk), - .spi0_csn_0_o (spi_csn), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi_miso), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (spi_mosi), - .spi1_clk_i (1'b0), - .spi1_clk_o (), - .spi1_csn_0_o (), - .spi1_csn_1_o (), - .spi1_csn_2_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (), - .spi1_sdo_o (), - .tx_clk_out_n (tx_clk_out_n), - .tx_clk_out_p (tx_clk_out_p), - .tx_data_out_n (tx_data_out_n), - .tx_data_out_p (tx_data_out_p), - .tx_frame_out_n (tx_frame_out_n), - .tx_frame_out_p (tx_frame_out_p), - .enable (enable), - .txnrx (txnrx), - .up_enable (gpio_o[47]), - .up_txnrx (gpio_o[48])); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/imageon/zc706/Makefile b/projects/imageon/zc706/Makefile deleted file mode 100644 index 59a4ac972..000000000 --- a/projects/imageon/zc706/Makefile +++ /dev/null @@ -1,19 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := imageon_zc706 - -M_DEPS += ../common/imageon_bd.tcl -M_DEPS += ../../common/zc706/zc706_system_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v - -LIB_DEPS += axi_clkgen -LIB_DEPS += axi_dmac -LIB_DEPS += axi_hdmi_rx -LIB_DEPS += axi_hdmi_tx -LIB_DEPS += axi_spdif_rx -LIB_DEPS += axi_spdif_tx - -include ../../scripts/project-xilinx.mk diff --git a/projects/imageon/zc706/system_bd.tcl b/projects/imageon/zc706/system_bd.tcl deleted file mode 100644 index 38ae53a6c..000000000 --- a/projects/imageon/zc706/system_bd.tcl +++ /dev/null @@ -1,4 +0,0 @@ - -source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source ../common/imageon_bd.tcl - diff --git a/projects/imageon/zc706/system_constr.xdc b/projects/imageon/zc706/system_constr.xdc deleted file mode 100644 index 9b1b1257d..000000000 --- a/projects/imageon/zc706/system_constr.xdc +++ /dev/null @@ -1,81 +0,0 @@ - -# fmc hdmi rx (adv7611) - -set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_clk] ; ## G2 FMC_LPC_CLK1_M2C_P -set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_spdif] ; ## H29 FMC_LPC_LA24_N -set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[0]] ; ## H32 FMC_LPC_LA28_N -set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[1]] ; ## H31 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[2]] ; ## G31 FMC_LPC_LA29_N -set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[3]] ; ## C27 FMC_LPC_LA27_N -set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[4]] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[5]] ; ## G30 FMC_LPC_LA29_P -set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[6]] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[7]] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[8]] ; ## H38 FMC_LPC_LA32_N -set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[9]] ; ## H37 FMC_LPC_LA32_P -set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[10]] ; ## G37 FMC_LPC_LA33_N -set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[11]] ; ## G36 FMC_LPC_LA33_P -set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[12]] ; ## H35 FMC_LPC_LA30_N -set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[13]] ; ## H34 FMC_LPC_LA30_P -set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[14]] ; ## G34 FMC_LPC_LA31_N -set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_rx_data[15]] ; ## G33 FMC_LPC_LA31_P -set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS25} [get_ports hdmi_rx_int] ; ## D08 FMC_LPC_LA01_CC_P - -# fmc hdmi tx (adv7511) - -set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_clk] ; ## G3 FMC_LPC_CLK1_M2C_N -set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports hdmi_tx_spdif] ; ## H28 FMC_LPC_LA24_P -set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[0]] ; ## G28 FMC_LPC_LA25_N -set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[1]] ; ## G27 FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[2]] ; ## H26 FMC_LPC_LA21_N -set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[3]] ; ## D24 FMC_LPC_LA23_N -set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[4]] ; ## H25 FMC_LPC_LA21_P -set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[5]] ; ## G25 FMC_LPC_LA22_N -set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[6]] ; ## C23 FMC_LPC_LA18_CC_N -set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[7]] ; ## D23 FMC_LPC_LA23_P -set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[8]] ; ## G24 FMC_LPC_LA22_P -set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[9]] ; ## H23 FMC_LPC_LA19_N -set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[10]] ; ## C22 FMC_LPC_LA18_CC_P -set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[11]] ; ## D21 FMC_LPC_LA17_CC_N -set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[12]] ; ## H22 FMC_LPC_LA19_P -set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[13]] ; ## G22 FMC_LPC_LA20_N -set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[14]] ; ## D20 FMC_LPC_LA17_CC_P -set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports hdmi_tx_data[15]] ; ## G21 FMC_LPC_LA20_P - -# iic pins - -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports hdmi_iic_scl] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports hdmi_iic_sda] ; ## G19 FMC_LPC_LA16_N -set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports hdmi_iic_rstn] ; ## D9 FMC_LPC_LA01_CC_N - -# clock definition - -create_clock -period 6.000 -name hdmi_rx_clk [get_ports hdmi_rx_clk] - -# default constraints - -# iic - -set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl] -set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda] - -# gpio (switches, leds and such) - -set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0 -set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1 -set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2 -set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3 -set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## GPIO_SW_LEFT -set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]] ; ## GPIO_SW_CENTER -set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## GPIO_SW_RIGHT - -set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## GPIO_LED_LEFT -set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]] ; ## GPIO_LED_CENTER -set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## GPIO_LED_RIGHT -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]] ; ## GPIO_LED_0 - -set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]] ; ## XADC_GPIO_0 -set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[12]] ; ## XADC_GPIO_1 -set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]] ; ## XADC_GPIO_2 -set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]] ; ## XADC_GPIO_3 - diff --git a/projects/imageon/zc706/system_project.tcl b/projects/imageon/zc706/system_project.tcl deleted file mode 100644 index 7b070a333..000000000 --- a/projects/imageon/zc706/system_project.tcl +++ /dev/null @@ -1,14 +0,0 @@ -# load script - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_xilinx imageon_zc706 -adi_project_files imageon_zc706 [list \ - "system_top.v" \ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ - "system_constr.xdc" ] - -adi_project_run imageon_zc706 - diff --git a/projects/imageon/zc706/system_top.v b/projects/imageon/zc706/system_top.v deleted file mode 100644 index 8805ff1d6..000000000 --- a/projects/imageon/zc706/system_top.v +++ /dev/null @@ -1,173 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [14:0] gpio_bd, - - inout iic_scl, - inout iic_sda, - - input hdmi_rx_clk, - input [15:0] hdmi_rx_data, - inout hdmi_rx_int, - input hdmi_rx_spdif, - - output hdmi_tx_clk, - output [15:0] hdmi_tx_data, - output hdmi_tx_spdif, - - inout hdmi_iic_scl, - inout hdmi_iic_sda, - inout hdmi_iic_rstn); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - - assign gpio_i[63:34] = gpio_o[63:34]; - assign gpio_i[31:15] = gpio_o[31:15]; - - // instantiations - - ad_iobuf #(.DATA_WIDTH(2)) i_gpio ( - .dio_t (gpio_t[33:32]), - .dio_i (gpio_o[33:32]), - .dio_o (gpio_i[33:32]), - .dio_p ({hdmi_iic_rstn, hdmi_rx_int})); - - ad_iobuf #(.DATA_WIDTH(15)) i_gpio_bd ( - .dio_t (gpio_t[14:0]), - .dio_i (gpio_o[14:0]), - .dio_o (gpio_i[14:0]), - .dio_p (gpio_bd)); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_rx_clk (hdmi_rx_clk), - .hdmi_rx_data (hdmi_rx_data), - .hdmi_tx_clk (hdmi_tx_clk), - .hdmi_tx_data (hdmi_tx_data), - .iic_imageon_scl_io (hdmi_iic_scl), - .iic_imageon_sda_io (hdmi_iic_sda), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .ps_intr_08 (1'b0), - .ps_intr_09 (1'b0), - .ps_intr_10 (1'b0), - .ps_intr_13 (1'b0), - .spdif_rx (hdmi_rx_spdif), - .spdif_tx (hdmi_tx_spdif), - .spi0_clk_i (1'b0), - .spi0_clk_o (), - .spi0_csn_0_o (), - .spi0_csn_1_o (), - .spi0_csn_2_o (), - .spi0_csn_i (1'b1), - .spi0_sdi_i (1'b0), - .spi0_sdo_i (1'b0), - .spi0_sdo_o (), - .spi1_clk_i (1'b0), - .spi1_clk_o (), - .spi1_csn_0_o (), - .spi1_csn_1_o (), - .spi1_csn_2_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (1'b0), - .spi1_sdo_o ()); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/m2k/zed/Makefile b/projects/m2k/zed/Makefile deleted file mode 100644 index fdf85bcda..000000000 --- a/projects/m2k/zed/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -#################################################################################### -## Copyright 2018(c) Analog Devices, Inc. -## Auto-generated, do not modify! -#################################################################################### - -PROJECT_NAME := m2k_fmc_zed - -M_DEPS += ../common/m2k_spi.v -M_DEPS += ../common/m2k_bd.tcl -M_DEPS += ../../common/zed/zed_system_constr.xdc -M_DEPS += ../../common/zed/zed_system_bd.tcl -M_DEPS += ../../../library/xilinx/common/ad_iobuf.v - -LIB_DEPS += axi_ad9963 -LIB_DEPS += axi_adc_decimate -LIB_DEPS += axi_adc_trigger -LIB_DEPS += axi_clkgen -LIB_DEPS += axi_dac_interpolate -LIB_DEPS += axi_dmac -LIB_DEPS += axi_hdmi_tx -LIB_DEPS += axi_i2s_adi -LIB_DEPS += axi_logic_analyzer -LIB_DEPS += axi_rd_wr_combiner -LIB_DEPS += axi_spdif_tx -LIB_DEPS += util_extract -LIB_DEPS += util_i2c_mixer -LIB_DEPS += util_var_fifo - -include ../../scripts/project-xilinx.mk diff --git a/projects/m2k/zed/system_bd.tcl b/projects/m2k/zed/system_bd.tcl deleted file mode 100644 index e04a871d2..000000000 --- a/projects/m2k/zed/system_bd.tcl +++ /dev/null @@ -1,42 +0,0 @@ - -source ../../common/zed/zed_system_bd.tcl -source ../common/m2k_bd.tcl - -# Use the 100 MHz clock for video DMA, the AXI interface clock is to slow for -# this in this project. - -set video_dma_clocks [list \ - axi_hp0_interconnect/ACLK \ - axi_hp0_interconnect/M00_ACLK \ - axi_hp0_interconnect/S00_ACLK \ - sys_ps7/S_AXI_HP0_ACLK \ - axi_hdmi_dma/m_axi_mm2s_aclk \ - axi_hdmi_dma/m_axis_mm2s_aclk \ - axi_hdmi_core/vdma_clk -] - -set video_dma_resets [list \ - axi_hp0_interconnect/ARESETN \ - axi_hp0_interconnect/M00_ARESETN \ - axi_hp0_interconnect/S00_ARESETN \ -] - -ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 100.0 - -ad_ip_parameter axi_hdmi_clkgen CONFIG.VCO_DIV 4 -ad_ip_parameter axi_hdmi_clkgen CONFIG.VCO_MUL 37.125 -ad_ip_parameter axi_hdmi_clkgen CONFIG.CLK0_DIV 6.250 - -ad_ip_instance proc_sys_reset video_dma_reset -ad_connect sys_ps7/FCLK_CLK1 video_dma_reset/slowest_sync_clk -ad_connect sys_rstgen/peripheral_aresetn video_dma_reset/ext_reset_in - -foreach clk $video_dma_clocks { - ad_disconnect /sys_cpu_clk $clk - ad_connect $clk sys_ps7/FCLK_CLK1 -} - -foreach rst $video_dma_resets { - ad_disconnect /sys_cpu_resetn $rst - ad_connect $rst video_dma_reset/peripheral_aresetn -} diff --git a/projects/m2k/zed/system_constr.xdc b/projects/m2k/zed/system_constr.xdc deleted file mode 100644 index 91914366d..000000000 --- a/projects/m2k/zed/system_constr.xdc +++ /dev/null @@ -1,70 +0,0 @@ -# the board can be used at 1.8V, 2.5V, 3.3V. 3.3V is the recommended setting -# given that the zedboard default configuration is for 2.5V, this voltage is used in the constraint file - -set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports en_power_analog] ; ## A16 FMC_LPC_LA28_P -set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25} [get_ports ad9963_resetn] ; ## G33 FMC_LPC_LA31_P - -set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports adf4360_cs] ; ## G36 FMC_LPC_LA33_P -set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25} [get_ports ad9963_csn] ; ## G34 FMC_LPC_LA31_N -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## G30 FMC_LPC_LA29_P -set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## G31 FMC_LPC_LA29_N - -set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25} [get_ports trigger_bd[0]] ; ## C22 FMC_LPC_LA18_CC_P -set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports trigger_bd[1]] ; ## C23 FMC_LPC_LA18_CC_N - -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports data_bd[0]] ; ## D20 FMC_LPC_LA17_CC_P -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports data_bd[1]] ; ## D21 FMC_LPC_LA17_CC_N -set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports data_bd[2]] ; ## D17 FMC_LPC_LA13_P -set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports data_bd[3]] ; ## D18 FMC_LPC_LA13_N -set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports data_bd[4]] ; ## D23 FMC_LPC_LA23_P -set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports data_bd[5]] ; ## D24 FMC_LPC_LA23_N -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports data_bd[6]] ; ## D26 FMC_LPC_LA26_P -set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports data_bd[7]] ; ## D27 FMC_LPC_LA26_N -set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports data_bd[8]] ; ## C10 FMC_LPC_LA06_P -set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports data_bd[9]] ; ## C11 FMC_LPC_LA06_N -set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports data_bd[10]] ; ## C14 FMC_LPC_LA10_P -set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports data_bd[11]] ; ## C15 FMC_LPC_LA10_N -set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports data_bd[12]] ; ## C18 FMC_LPC_LA14_P -set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports data_bd[13]] ; ## C19 FMC_LPC_LA14_N -set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports data_bd[14]] ; ## C26 FMC_LPC_LA27_P -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports data_bd[15]] ; ## C27 FMC_LPC_LA27_P - -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports rx_clk] ; ## G07 FMC_LPC_LA01_CC_P -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports rxiq] ; ## G27 FMC_LPC_LA25_P -set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports rxd[0]] ; ## H07 FMC_LPC_LA02_P -set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports rxd[1]] ; ## H08 FMC_LPC_LA02_N -set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports rxd[2]] ; ## H10 FMC_LPC_LA04_P -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports rxd[3]] ; ## H11 FMC_LPC_LA04_N -set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports rxd[4]] ; ## H13 FMC_LPC_LA07_P -set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports rxd[5]] ; ## H14 FMC_LPC_LA07_N -set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports rxd[6]] ; ## H16 FMC_LPC_LA11_P -set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports rxd[7]] ; ## H17 FMC_LPC_LA11_N -set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports rxd[8]] ; ## H19 FMC_LPC_LA15_P -set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports rxd[9]] ; ## H20 FMC_LPC_LA15_N -set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports rxd[10]] ; ## H22 FMC_LPC_LA19_P -set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports rxd[11]] ; ## H23 FMC_LPC_LA19_N - -set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports tx_clk] ; ## G06 FMC_LPC_LA00_CC_P -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports txiq] ; ## G28 FMC_LPC_LA25_N -set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports txd[0]] ; ## G09 FMC_LPC_LA03_P -set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports txd[1]] ; ## G10 FMC_LPC_LA03_N -set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports txd[2]] ; ## G12 FMC_LPC_LA08_P -set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports txd[3]] ; ## G13 FMC_LPC_LA08_N -set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports txd[4]] ; ## G15 FMC_LPC_LA12_P -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports txd[5]] ; ## G16 FMC_LPC_LA12_N -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports txd[6]] ; ## G18 FMC_LPC_LA16_P -set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports txd[7]] ; ## G19 FMC_LPC_LA16_N -set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports txd[8]] ; ## G21 FMC_LPC_LA20_P -set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports txd[9]] ; ## G22 FMC_LPC_LA20_N -set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports txd[10]] ; ## G24 FMC_LPC_LA22_P -set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports txd[11]] ; ## G25 FMC_LPC_LA22_N - -create_clock -name rx_clk -period 10.00 [get_ports rx_clk] -create_clock -name tx_clk -period 6.66 [get_ports tx_clk] - -create_clock -name data_clk -period 12.5 [get_ports data_bd[0]] - -set_clock_groups -name exclusive_ -physically_exclusive \ --group [get_clocks data_clk] -group [get_clocks clk_fpga_2] - -set_false_path -from [get_clocks data_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/data_m1_reg[0]/D}] diff --git a/projects/m2k/zed/system_project.tcl b/projects/m2k/zed/system_project.tcl deleted file mode 100644 index c9d9cff23..000000000 --- a/projects/m2k/zed/system_project.tcl +++ /dev/null @@ -1,15 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl -source $ad_hdl_dir/projects/scripts/adi_board.tcl - -adi_project_xilinx m2k_fmc_zed -adi_project_files m2k_fmc_zed [list \ - "../common/m2k_spi.v" \ - "system_top.v" \ - "system_constr.xdc" \ - "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ - "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] - -adi_project_run m2k_fmc_zed - diff --git a/projects/m2k/zed/system_top.v b/projects/m2k/zed/system_top.v deleted file mode 100644 index 28007ff9e..000000000 --- a/projects/m2k/zed/system_top.v +++ /dev/null @@ -1,276 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. -// -// In this HDL repository, there are many different and unique modules, consisting -// of various HDL (Verilog or VHDL) components. The individual modules are -// developed independently, and may be accompanied by separate and unique license -// terms. -// -// The user should read each of these license terms, and understand the -// freedoms and responsibilities that he or she has by using this source/core. -// -// This core is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR -// A PARTICULAR PURPOSE. -// -// Redistribution and use of source or resulting binaries, with or without modification -// of this file, are permitted under one of the following two license terms: -// -// 1. The GNU General Public License version 2 as published by the -// Free Software Foundation, which can be found in the top level directory -// of this repository (LICENSE_GPL2), and also online at: -// -// -// OR -// -// 2. An ADI specific BSD license, which can be found in the top level directory -// of this repository (LICENSE_ADIBSD), and also on-line at: -// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD -// This will allow to generate bit files and not release the source code, -// as long as it attaches to an ADI device. -// -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - inout [14:0] ddr_addr, - inout [ 2:0] ddr_ba, - inout ddr_cas_n, - inout ddr_ck_n, - inout ddr_ck_p, - inout ddr_cke, - inout ddr_cs_n, - inout [ 3:0] ddr_dm, - inout [31:0] ddr_dq, - inout [ 3:0] ddr_dqs_n, - inout [ 3:0] ddr_dqs_p, - inout ddr_odt, - inout ddr_ras_n, - inout ddr_reset_n, - inout ddr_we_n, - - inout fixed_io_ddr_vrn, - inout fixed_io_ddr_vrp, - inout [53:0] fixed_io_mio, - inout fixed_io_ps_clk, - inout fixed_io_ps_porb, - inout fixed_io_ps_srstb, - - inout [31:0] gpio_bd, - - output hdmi_out_clk, - output hdmi_vsync, - output hdmi_hsync, - output hdmi_data_e, - output [15:0] hdmi_data, - - output i2s_mclk, - output i2s_bclk, - output i2s_lrclk, - output i2s_sdata_out, - input i2s_sdata_in, - - output spdif, - - inout [ 1:0] iic_mux_scl, - inout [ 1:0] iic_mux_sda, - - input otg_vbusoc, - - inout [15:0] data_bd, - inout [ 1:0] trigger_bd, - - input rx_clk, - input rxiq, - input [11:0] rxd, - input tx_clk, - output txiq, - output [11:0] txd, - - output ad9963_resetn, - output ad9963_csn, - output adf4360_cs, - output spi_clk, - inout spi_sdio, - - output en_power_analog, - - inout iic_scl, - inout iic_sda); - - // internal signals - - wire [63:0] gpio_i; - wire [63:0] gpio_o; - wire [63:0] gpio_t; - wire [ 1:0] iic_mux_scl_i_s; - wire [ 1:0] iic_mux_scl_o_s; - wire iic_mux_scl_t_s; - wire [ 1:0] iic_mux_sda_i_s; - wire [ 1:0] iic_mux_sda_o_s; - wire iic_mux_sda_t_s; - - wire [15:0] data_i; - wire [15:0] data_o; - wire [15:0] data_t; - - wire [ 1:0] trigger_i; - wire [ 1:0] trigger_o; - wire [ 1:0] trigger_t; - - wire [ 1:0] spi0_csn; - wire spi0_clk; - wire spi0_mosi; - wire spi0_miso; - - assign ad9963_resetn = gpio_o[32]; - assign en_power_analog = gpio_o[33]; - - assign ad9963_csn = spi0_csn[0]; - assign adf4360_cs = spi0_csn[1]; - assign spi_clk = spi0_clk; - assign spi_mosi = spi0_mosi; - assign spi0_miso = spi_miso; - - assign gpio_i[63:32] = gpio_o[63:32]; - - // instantiations - - ad_iobuf #( - .DATA_WIDTH(32) - ) i_iobuf ( - .dio_t(gpio_t[31:0]), - .dio_i(gpio_o[31:0]), - .dio_o(gpio_i[31:0]), - .dio_p(gpio_bd)); - - ad_iobuf #( - .DATA_WIDTH(2) - ) i_iic_mux_scl ( - .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), - .dio_i(iic_mux_scl_o_s), - .dio_o(iic_mux_scl_i_s), - .dio_p(iic_mux_scl)); - - ad_iobuf #( - .DATA_WIDTH(2) - ) i_iic_mux_sda ( - .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), - .dio_i(iic_mux_sda_o_s), - .dio_o(iic_mux_sda_i_s), - .dio_p(iic_mux_sda)); - - ad_iobuf #( - .DATA_WIDTH(16) - ) i_data_bd ( - .dio_t(data_t[15:0]), - .dio_i(data_o[15:0]), - .dio_o(data_i[15:0]), - .dio_p(data_bd)); - - ad_iobuf #( - .DATA_WIDTH(2) - ) i_trigger_bd ( - .dio_t(trigger_t[1:0]), - .dio_i(trigger_o[1:0]), - .dio_o(trigger_i[1:0]), - .dio_p(trigger_bd)); - - m2k_spi i_m2k_spi ( - .ad9963_csn (ad9963_csn), - .adf4360_cs (adf4360_cs), - .spi_clk (spi_clk), - .spi_mosi (spi_mosi), - .spi_miso (spi_miso), - .spi_sdio (spi_sdio)); - - system_wrapper i_system_wrapper ( - .ddr_addr (ddr_addr), - .ddr_ba (ddr_ba), - .ddr_cas_n (ddr_cas_n), - .ddr_ck_n (ddr_ck_n), - .ddr_ck_p (ddr_ck_p), - .ddr_cke (ddr_cke), - .ddr_cs_n (ddr_cs_n), - .ddr_dm (ddr_dm), - .ddr_dq (ddr_dq), - .ddr_dqs_n (ddr_dqs_n), - .ddr_dqs_p (ddr_dqs_p), - .ddr_odt (ddr_odt), - .ddr_ras_n (ddr_ras_n), - .ddr_reset_n (ddr_reset_n), - .ddr_we_n (ddr_we_n), - .fixed_io_ddr_vrn (fixed_io_ddr_vrn), - .fixed_io_ddr_vrp (fixed_io_ddr_vrp), - .fixed_io_mio (fixed_io_mio), - .fixed_io_ps_clk (fixed_io_ps_clk), - .fixed_io_ps_porb (fixed_io_ps_porb), - .fixed_io_ps_srstb (fixed_io_ps_srstb), - .gpio_i (gpio_i), - .gpio_o (gpio_o), - .gpio_t (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .i2s_bclk (i2s_bclk), - .i2s_lrclk (i2s_lrclk), - .i2s_mclk (i2s_mclk), - .i2s_sdata_in (i2s_sdata_in), - .i2s_sdata_out (i2s_sdata_out), - .iic_fmc_scl_io (iic_scl), - .iic_fmc_sda_io (iic_sda), - .iic_mux_scl_i (iic_mux_scl_i_s), - .iic_mux_scl_o (iic_mux_scl_o_s), - .iic_mux_scl_t (iic_mux_scl_t_s), - .iic_mux_sda_i (iic_mux_sda_i_s), - .iic_mux_sda_o (iic_mux_sda_o_s), - .iic_mux_sda_t (iic_mux_sda_t_s), - .data_i(data_i), - .data_o(data_o), - .data_t(data_t), - .trigger_i(trigger_i), - .trigger_o(trigger_o), - .trigger_t(trigger_t), - .rx_clk(rx_clk), - .rxiq(rxiq), - .rxd(rxd), - .tx_clk(tx_clk), - .txiq(txiq), - .txd(txd), - .ps_intr_00 (1'b0), - .ps_intr_01 (1'b0), - .ps_intr_02 (1'b0), - .ps_intr_03 (1'b0), - .ps_intr_04 (1'b0), - .ps_intr_05 (1'b0), - .ps_intr_06 (1'b0), - .ps_intr_07 (1'b0), - .spi0_clk_i (spi0_clk), - .spi0_clk_o (spi0_clk), - .spi0_csn_0_o (spi0_csn[0]), - .spi0_csn_1_o (spi0_csn[1]), - .spi0_csn_i (1'b1), - .spi0_sdi_i (spi0_miso), - .spi0_sdo_i (spi0_mosi), - .spi0_sdo_o (spi0_mosi), - .spi1_clk_i (1'b0), - .spi1_clk_o (), - .spi1_csn_0_o (), - .spi1_csn_1_o (), - .spi1_csn_i (1'b1), - .spi1_sdi_i (1'b0), - .spi1_sdo_i (1'b0), - .spi1_sdo_o (), - .otg_vbusoc (otg_vbusoc), - .spdif (spdif)); - -endmodule - -// *************************************************************************** -// ***************************************************************************