ad_axis_inf_rx: Initialize output ports to avoid X propagation in simulation
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@ -49,9 +49,9 @@ module ad_axis_inf_rx #(
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// xilinx interface
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output reg inf_valid,
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output reg inf_last,
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output reg [(DATA_WIDTH-1):0] inf_data,
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output reg inf_valid = 1'b0,
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output reg inf_last = 1'b0,
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output reg [(DATA_WIDTH-1):0] inf_data = {DATA_WIDTH{1'b0}},
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input inf_ready);
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// internal registers
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