zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

adrv9371/a10soc: Integrate the avl_dacfifo into project

main
Istvan Csomortani 2017-04-21 13:27:35 +03:00
parent 180a80493b
commit 6ed721ee66
4 changed files with 28 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
projects/adrv9371x/a10soc/Makefile
View File

@ -97,13 +97,12 @@ M_DEPS += ../../../library/util_upack/util_upack.v
M_DEPS += ../../../library/util_upack/util_upack_dmx.v M_DEPS += ../../../library/util_upack/util_upack_dmx.v
M_DEPS += ../../../library/util_upack/util_upack_dsf.v M_DEPS += ../../../library/util_upack/util_upack_dsf.v
M_DEPS += ../../../library/util_upack/util_upack_hw.tcl M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo.v M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_hw.tcl
M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo.v
M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo_constr.sdc M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_rd.v
M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo_dac.v M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_wr.v
M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo_hw.tcl M_DEPS += ../../../library/common/util_dacfifo_bypass.v
M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo_rd.v M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_constr.sdc
M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
M_ALTERA := quartus_sh --64bit -t M_ALTERA := quartus_sh --64bit -t

2
projects/adrv9371x/a10soc/system_qsys.tcl
View File

@ -1,5 +1,5 @@
set dac_fifo_name axi_ad9371_tx_fifo set dac_fifo_name avl_ad9371_tx_fifo
set dac_fifo_address_width 10 set dac_fifo_address_width 10
set dac_data_width 128 set dac_data_width 128
set dac_dma_data_width 128 set dac_dma_data_width 128

26
projects/adrv9371x/common/adrv9371x_qsys.tcl
View File

@ -180,13 +180,13 @@ add_connection axi_ad9371.adc_os_ch_1 axi_ad9371_rx_os_cpack.adc_ch_1
# dac & adc fifos # dac & adc fifos
# #
add_interface tx_fifo_bypass conduit end add_interface tx_fifo_bypass conduit end
set_interface_property tx_fifo_bypass EXPORT_OF axi_ad9371_tx_fifo.if_bypass set_interface_property tx_fifo_bypass EXPORT_OF avl_ad9371_tx_fifo.if_bypass
add_connection axi_ad9371_tx_xcvr.if_up_rst axi_ad9371_tx_fifo.if_dac_rst add_connection axi_ad9371_tx_xcvr.if_up_rst avl_ad9371_tx_fifo.if_dac_rst
add_connection avl_ad9371_tx_xcvr.core_clk axi_ad9371_tx_fifo.if_dac_clk add_connection avl_ad9371_tx_xcvr.core_clk avl_ad9371_tx_fifo.if_dac_clk
add_connection axi_ad9371_tx_upack.if_dac_valid axi_ad9371_tx_fifo.if_dac_valid add_connection axi_ad9371_tx_upack.if_dac_valid avl_ad9371_tx_fifo.if_dac_valid
add_connection axi_ad9371_tx_fifo.if_dac_data axi_ad9371_tx_upack.if_dac_data add_connection avl_ad9371_tx_fifo.if_dac_data axi_ad9371_tx_upack.if_dac_data
add_connection axi_ad9371_tx_fifo.if_dac_dunf axi_ad9371.if_dac_dunf add_connection avl_ad9371_tx_fifo.if_dac_dunf axi_ad9371.if_dac_dunf
add_instance axi_ad9371_rx_fifo util_adcfifo 1.0 add_instance axi_ad9371_rx_fifo util_adcfifo 1.0
set_instance_parameter_value axi_ad9371_rx_fifo {ADC_DATA_WIDTH} {64} set_instance_parameter_value axi_ad9371_rx_fifo {ADC_DATA_WIDTH} {64}
@ -229,14 +229,14 @@ set_instance_parameter_value axi_ad9371_tx_dma {CYCLIC} {1}
set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_DEST} {1} set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_DEST} {1}
set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_SRC} {0} set_instance_parameter_value axi_ad9371_tx_dma {DMA_TYPE_SRC} {0}
set_instance_parameter_value axi_ad9371_tx_dma {FIFO_SIZE} {16} set_instance_parameter_value axi_ad9371_tx_dma {FIFO_SIZE} {16}
add_connection sys_dma_clk.clk axi_ad9371_tx_fifo.if_dma_clk add_connection sys_dma_clk.clk avl_ad9371_tx_fifo.if_dma_clk
add_connection sys_dma_clk.clk_reset axi_ad9371_tx_fifo.if_dma_rst add_connection sys_dma_clk.clk_reset avl_ad9371_tx_fifo.if_dma_rst
add_connection sys_dma_clk.clk axi_ad9371_tx_dma.if_m_axis_aclk add_connection sys_dma_clk.clk axi_ad9371_tx_dma.if_m_axis_aclk
add_connection axi_ad9371_tx_dma.if_m_axis_valid axi_ad9371_tx_fifo.if_dma_valid add_connection axi_ad9371_tx_dma.if_m_axis_valid avl_ad9371_tx_fifo.if_dma_valid
add_connection axi_ad9371_tx_dma.if_m_axis_data axi_ad9371_tx_fifo.if_dma_data add_connection axi_ad9371_tx_dma.if_m_axis_data avl_ad9371_tx_fifo.if_dma_data
add_connection axi_ad9371_tx_dma.if_m_axis_last axi_ad9371_tx_fifo.if_dma_xfer_last add_connection axi_ad9371_tx_dma.if_m_axis_last avl_ad9371_tx_fifo.if_dma_xfer_last
add_connection axi_ad9371_tx_dma.if_m_axis_xfer_req axi_ad9371_tx_fifo.if_dma_xfer_req add_connection axi_ad9371_tx_dma.if_m_axis_xfer_req avl_ad9371_tx_fifo.if_dma_xfer_req
add_connection axi_ad9371_tx_fifo.if_dma_ready axi_ad9371_tx_dma.if_m_axis_ready add_connection avl_ad9371_tx_fifo.if_dma_ready axi_ad9371_tx_dma.if_m_axis_ready
add_connection sys_clk.clk axi_ad9371_tx_dma.s_axi_clock add_connection sys_clk.clk axi_ad9371_tx_dma.s_axi_clock
add_connection sys_clk.clk_reset axi_ad9371_tx_dma.s_axi_reset add_connection sys_clk.clk_reset axi_ad9371_tx_dma.s_axi_reset
add_connection sys_dma_clk.clk axi_ad9371_tx_dma.m_src_axi_clock add_connection sys_dma_clk.clk axi_ad9371_tx_dma.m_src_axi_clock

16
projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl
View File

@ -60,16 +60,16 @@ set_interface_property sys_ddr_mem EXPORT_OF sys_ddr4_cntrl.mem_conduit_end
add_interface sys_ddr_status conduit end add_interface sys_ddr_status conduit end
set_interface_property sys_ddr_status EXPORT_OF sys_ddr4_cntrl.status_conduit_end set_interface_property sys_ddr_status EXPORT_OF sys_ddr4_cntrl.status_conduit_end
add_instance $dac_fifo_name axi_dacfifo 1.0 add_instance $dac_fifo_name avl_dacfifo 1.0
set_instance_parameter_value $dac_fifo_name {DAC_DATA_WIDTH} $dac_data_width set_instance_parameter_value $dac_fifo_name {DAC_DATA_WIDTH} $dac_data_width
set_instance_parameter_value $dac_fifo_name {DMA_DATA_WIDTH} $dac_dma_data_width set_instance_parameter_value $dac_fifo_name {DMA_DATA_WIDTH} $dac_dma_data_width
set_instance_parameter_value $dac_fifo_name {AXI_DATA_WIDTH} {512} set_instance_parameter_value $dac_fifo_name {AVL_DATA_WIDTH} {512}
set_instance_parameter_value $dac_fifo_name {AXI_ADDRESS} {0} set_instance_parameter_value $dac_fifo_name {AVL_BASE_ADDRESS} {0}
set_instance_parameter_value $dac_fifo_name {AXI_ADDRESS_LIMIT} {0x7fffffff} set_instance_parameter_value $dac_fifo_name {AVL_ADDRESS_LIMIT} {0x1fffffff}
add_connection sys_clk.clk_reset sys_ddr4_cntrl.global_reset_reset_sink add_connection sys_clk.clk_reset sys_ddr4_cntrl.global_reset_reset_sink
add_connection sys_ddr4_cntrl.emif_usr_reset_reset_source $dac_fifo_name.axi_reset_n add_connection sys_ddr4_cntrl.emif_usr_reset_reset_source $dac_fifo_name.avl_reset
add_connection sys_ddr4_cntrl.emif_usr_clk_clock_source $dac_fifo_name.axi_clock add_connection sys_ddr4_cntrl.emif_usr_clk_clock_source $dac_fifo_name.avl_clock
add_connection $dac_fifo_name.m_axi sys_ddr4_cntrl.ctrl_amm_avalon_slave_0 add_connection $dac_fifo_name.amm_ddr sys_ddr4_cntrl.ctrl_amm_avalon_slave_0
set_connection_parameter_value $dac_fifo_name.m_axi/sys_ddr4_cntrl.ctrl_amm_avalon_slave_0 baseAddress {0x0} set_connection_parameter_value $dac_fifo_name.amm_ddr/sys_ddr4_cntrl.ctrl_amm_avalon_slave_0 baseAddress {0x0}