From 6f4235a11b53dafae68b4f18f80c2f138e2938f4 Mon Sep 17 00:00:00 2001 From: PopPaul2021 <93918446+PopPaul2021@users.noreply.github.com> Date: Mon, 13 May 2024 19:18:22 +0300 Subject: [PATCH] docs: page for AD777x IP (#1324) Signed-off-by: Jorge Marques Signed-off-by: PopPaul2021 --- docs/library/axi_ad777x/block_diagram.svg | 4 + .../axi_ad777x/detailed_architecture.svg | 4 + docs/library/axi_ad777x/index.rst | 163 ++++++++++++++++++ 3 files changed, 171 insertions(+) create mode 100644 docs/library/axi_ad777x/block_diagram.svg create mode 100644 docs/library/axi_ad777x/detailed_architecture.svg create mode 100644 docs/library/axi_ad777x/index.rst diff --git a/docs/library/axi_ad777x/block_diagram.svg b/docs/library/axi_ad777x/block_diagram.svg new file mode 100644 index 000000000..b1f995fda --- /dev/null +++ b/docs/library/axi_ad777x/block_diagram.svg @@ -0,0 +1,4 @@ + + + +
DMA_FIFO
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AXI_AD777x  IP architecture
AXI_AD777x  IP architecture
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adc_validText is not SVG - cannot display \ No newline at end of file diff --git a/docs/library/axi_ad777x/index.rst b/docs/library/axi_ad777x/index.rst new file mode 100644 index 000000000..808b99ff5 --- /dev/null +++ b/docs/library/axi_ad777x/index.rst @@ -0,0 +1,163 @@ +.. _axi_ad777x: + +AXI AD777x +================================================================================ + +.. hdl-component-diagram:: + +The :git-hdl:`AXI AD777x ` IP core +can be used to interface the :adi:`AD7770`, :adi:`AD7771` and :adi:`AD7779` +converters using an FPGA in 1, 2, or 4 data lines active. +More about the generic framework interfacing ADCs, that contains the +``up_adc_channel`` and ``up_adc_common modules``, can be read in :ref:`axi_adc`. + +Features +-------------------------------------------------------------------------------- + +* AXI based configuration +* CRC validation flag +* Configurable number of active data lines +* Real-time data header access +* Vivado and Quartus compatible + +Files +-------------------------------------------------------------------------------- + +.. list-table:: + :header-rows: 1 + + * - Name + - Description + * - :git-hdl:`library/axi_ad777x/axi_ad777x.v` + - Verilog source for the AXI AD777x. + * - :git-hdl:`library/axi_ad777x/axi_ad777x_if.v` + - Verilog source for the AXI AD777x interface module. + * - :git-hdl:`library/axi_ad777x/axi_ad777x_ip.tcl` + - TCL script to generate the Vivado IP-integrator project. + * - :git-hdl:`library/axi_ad777x/axi_ad777x_hw.tcl` + - TCL script to generate the Quartus IP-integrator project. + +Block Diagram +-------------------------------------------------------------------------------- + +.. image:: block_diagram.svg + :alt: AXI AD777x block diagram + +Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + + * - ID + - Core ID should be unique for each IP in the system + +Interface +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + + * - clk_in + - Input clock. + * - ready_in + - Input ready signal. + * - data_in + - Serial input data. + * - adc_dovf + - Data overflow input, from the DMA. + * - adc_clk + - This is the clock domain that most of the modules of the core run on. + * - adc_reset + - Output reset, on the adc_clk domain. + * - adc_enable_* + - Set when the channel is enabled, activated by software. + * - adc_valid_* + - Set when valid data is available on the bus. + * - adc_valid + - Set when valid data is available on the bus. + * - adc_data_* + - Channel parallel output data. + * - adc_crc_ch_mismatch + - Channels CRC mismatch flags register. + * - sync_adc_miso + - Syncronization input signal. + * - sync_adc_mosi + - Syncronization output signal. + * - s_axi + - Standard AXI Slave Memory Map interface. + +Detailed Architecture +-------------------------------------------------------------------------------- + +.. image:: detailed_architecture.svg + :alt: AXI AD777x detailed architecture + +Detailed Description +-------------------------------------------------------------------------------- + +The top module, axi_ad777x, instantiates: + +* The AD777x interface module +* The ADC channel register map +* The ADC common register map +* The AXI handling interface + +The AD777x interface module has as input the serial data lines, the ready_in +signal and the interface clock. Data is deserialized according to the number +of active lanes. The interface module also implements a parallel CRC check +algorithm. +The data from the interface module is processed by the adc channel module. +``up_adc_common`` module implements the ADC COMMON register map, allowing for +basic monitoring and control of the ADC. +``up_adc_channel`` module implements the ADC CHANNEL register map, allowing for +basic monitoring and control of the ADC's channel. + +Register Map +-------------------------------------------------------------------------------- + +.. hdl-regmap:: + :name: COMMON + :no-type-info: + +.. hdl-regmap:: + :name: ADC_COMMON + :no-type-info: + +.. hdl-regmap:: + :name: ADC_CHANNEL + :no-type-info: + +Design Guidelines +-------------------------------------------------------------------------------- + +The control of the ad777x chip is done through a SPI interface, which is needed +at system level. + +The *ADC interface signals* must be connected directly to the top file of the +design, as IO primitives are part of the IP. + +The example design uses a DMA to move the data from the output of the IP to +memory. + +If the data needs to be processed in HDL before moved to the memory, it can be +done at the output of the IP (at system level) or inside of the adc interface +module (at IP level). + +The example design uses a processor to program all the registers. If no +processor is available in your system, you can create your own IP starting from +the interface module. + +Software Guidelines +-------------------------------------------------------------------------------- + +Linux is suported using :git-linux:`/`. + +References +------------------------------------------------------------------------------- + +* :git-hdl:`library/axi_ad777x` +* :adi:`AD7770` +* :adi:`AD7771` +* :adi:`AD7779` +* :git-linux:`/` +* :xilinx:`Zynq-7000 SoC Overview ` +* :xilinx:`Zynq-7000 SoC Packaging and Pinout `