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fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack 

The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
main
Adrian Costina 2014-07-24 19:57:22 +03:00
parent a68f634de9
commit 7000897031
5 changed files with 1170 additions and 311 deletions
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586
library/util_adc_pack/util_adc_pack.v
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@ -43,18 +43,37 @@ module util_adc_pack (
clk,
chan_data_0,
chan_data_1,
chan_data_2,
chan_data_3,
chan_enable_0,
chan_enable_1,
chan_enable_2,
chan_enable_3,
chan_valid_0,
chan_data_0,
chan_enable_1,
chan_valid_1,
chan_data_1,
chan_enable_2,
chan_valid_2,
chan_data_2,
chan_enable_3,
chan_valid_3,
chan_data_3,
chan_enable_4,
chan_valid_4,
chan_data_4,
chan_enable_5,
chan_valid_5,
chan_data_5,
chan_enable_6,
chan_valid_6,
chan_data_6,
chan_enable_7,
chan_valid_7,
chan_data_7,
ddata,
dvalid,
@ -66,264 +85,361 @@ module util_adc_pack (
input clk;
input [15:0] chan_data_0;
input [15:0] chan_data_1;
input [15:0] chan_data_2;
input [15:0] chan_data_3;
input chan_enable_0;
input chan_enable_1;
input chan_enable_2;
input chan_enable_3;
input chan_valid_0;
input chan_valid_1;
input chan_valid_2;
input chan_valid_3;
input [15:0] chan_data_0;
output [63:0] ddata;
input chan_enable_1;
input chan_valid_1;
input [15:0] chan_data_1;
input chan_enable_2;
input chan_valid_2;
input [15:0] chan_data_2;
input chan_enable_3;
input chan_valid_3;
input [15:0] chan_data_3;
input chan_enable_4;
input chan_valid_4;
input [15:0] chan_data_4;
input chan_enable_5;
input chan_valid_5;
input [15:0] chan_data_5;
input chan_enable_6;
input chan_valid_6;
input [15:0] chan_data_6;
input chan_valid_7;
input chan_enable_7;
input [15:0] chan_data_7;
output [127:0] ddata;
output dvalid;
output dsync;
reg [47:0] adc_data_3_1110 = 'd0;
reg [47:0] adc_data_3_1101 = 'd0;
reg [47:0] adc_data_3_1011 = 'd0;
reg [47:0] adc_data_3_0111 = 'd0;
reg adc_iqcor_valid = 'd0;
reg adc_iqcor_valid_3 = 'd0;
reg adc_iqcor_sync = 'd0;
reg adc_iqcor_sync_3 = 'd0;
reg [63:0] adc_data = 'd0;
reg [63:0] adc_data_1110 = 'd0;
reg [63:0] adc_data_1101 = 'd0;
reg [63:0] adc_data_1011 = 'd0;
reg [63:0] adc_data_0111 = 'd0;
reg [ 1:0] adc_data_cnt = 'd0;
wire chan_valid;
wire [3:0] enable_cnt;
wire [2:0] enable_cnt_0;
wire [2:0] enable_cnt_1;
wire valid;
reg [127:0] packed_data = 0;
reg [63:0] temp_data_0 = 0;
reg [63:0] temp_data_1 = 0;
reg [7:0] path_enabled = 0;
reg [6:0] counter_0 = 0;
reg [7:0] en1 = 0;
reg [7:0] en2 = 0;
reg [7:0] en4 = 0;
reg [127:0] ddata = 0;
reg dvalid = 0;
reg chan_valid_d1 = 0;
assign dsync = adc_iqcor_sync;
assign dvalid = adc_iqcor_valid;
assign ddata = adc_data;
assign enable_cnt = enable_cnt_0 + enable_cnt_1;
assign enable_cnt_0 = chan_enable_0 + chan_enable_1 + chan_enable_2 + chan_enable_3;
assign enable_cnt_1 = chan_enable_4 + chan_enable_5 + chan_enable_6 + chan_enable_7;
assign chan_valid = chan_valid_0 | chan_valid_1 | chan_valid_2 | chan_valid_3 | chan_valid_4 | chan_valid_5 | chan_valid_6 | chan_valid_7 ;
assign dsync = dvalid;
assign valid = chan_valid_0 & chan_valid_1 & chan_valid_2 & chan_valid_3;
always @(posedge clk) begin
if (valid == 1'b1) begin
adc_iqcor_valid_3 <= adc_data_cnt[0] | adc_data_cnt[1];
adc_iqcor_sync_3 <= adc_data_cnt[0] & ~adc_data_cnt[1];
adc_data_3_1110[47:32] <= chan_data_3;
adc_data_3_1110[31:16] <= chan_data_2;
adc_data_3_1110[15: 0] <= chan_data_1;
adc_data_3_1101[47:32] <= chan_data_3;
adc_data_3_1101[31:16] <= chan_data_2;
adc_data_3_1101[15: 0] <= chan_data_0;
adc_data_3_1011[47:32] <= chan_data_3;
adc_data_3_1011[31:16] <= chan_data_1;
adc_data_3_1011[15: 0] <= chan_data_0;
adc_data_3_0111[47:32] <= chan_data_2;
adc_data_3_0111[31:16] <= chan_data_1;
adc_data_3_0111[15: 0] <= chan_data_0;
case (adc_data_cnt)
2'b11: begin
adc_data_1110[63:48] <= chan_data_3;
adc_data_1110[47:32] <= chan_data_2;
adc_data_1110[31:16] <= chan_data_1;
adc_data_1110[15: 0] <= adc_data_3_1110[47:32];
adc_data_1101[63:48] <= chan_data_3;
adc_data_1101[47:32] <= chan_data_2;
adc_data_1101[31:16] <= chan_data_0;
adc_data_1101[15: 0] <= adc_data_3_1101[47:32];
adc_data_1011[63:48] <= chan_data_3;
adc_data_1011[47:32] <= chan_data_1;
adc_data_1011[31:16] <= chan_data_0;
adc_data_1011[15: 0] <= adc_data_3_1011[47:32];
adc_data_0111[63:48] <= chan_data_2;
adc_data_0111[47:32] <= chan_data_1;
adc_data_0111[31:16] <= chan_data_0;
adc_data_0111[15: 0] <= adc_data_3_0111[47:32];
end
2'b10: begin
adc_data_1110[63:48] <= chan_data_2;
adc_data_1110[47:32] <= chan_data_1;
adc_data_1110[31:16] <= adc_data_3_1110[47:32];
adc_data_1110[15: 0] <= adc_data_3_1110[31:16];
adc_data_1101[63:48] <= chan_data_2;
adc_data_1101[47:32] <= chan_data_0;
adc_data_1101[31:16] <= adc_data_3_1101[47:32];
adc_data_1101[15: 0] <= adc_data_3_1101[31:16];
adc_data_1011[63:48] <= chan_data_1;
adc_data_1011[47:32] <= chan_data_0;
adc_data_1011[31:16] <= adc_data_3_1011[47:32];
adc_data_1011[15: 0] <= adc_data_3_1011[31:16];
adc_data_0111[63:48] <= chan_data_1;
adc_data_0111[47:32] <= chan_data_0;
adc_data_0111[31:16] <= adc_data_3_0111[47:32];
adc_data_0111[15: 0] <= adc_data_3_0111[31:16];
end
2'b01: begin
adc_data_1110[63:48] <= chan_data_1;
adc_data_1110[47:32] <= adc_data_3_1110[47:32];
adc_data_1110[31:16] <= adc_data_3_1110[31:16];
adc_data_1110[15: 0] <= adc_data_3_1110[15: 0];
adc_data_1101[63:48] <= chan_data_0;
adc_data_1101[47:32] <= adc_data_3_1101[47:32];
adc_data_1101[31:16] <= adc_data_3_1101[31:16];
adc_data_1101[15: 0] <= adc_data_3_1101[15: 0];
adc_data_1011[63:48] <= chan_data_0;
adc_data_1011[47:32] <= adc_data_3_1011[47:32];
adc_data_1011[31:16] <= adc_data_3_1011[31:16];
adc_data_1011[15: 0] <= adc_data_3_1011[15: 0];
adc_data_0111[63:48] <= chan_data_0;
adc_data_0111[47:32] <= adc_data_3_0111[47:32];
adc_data_0111[31:16] <= adc_data_3_0111[31:16];
adc_data_0111[15: 0] <= adc_data_3_0111[15: 0];
end
default:begin
adc_data_1110[63:48] <= 16'hdead;
adc_data_1110[47:32] <= 16'hdead;
adc_data_1110[31:16] <= 16'hdead;
adc_data_1110[15: 0] <= 16'hdead;
adc_data_1101[63:48] <= 16'hdead;
adc_data_1101[47:32] <= 16'hdead;
adc_data_1101[31:16] <= 16'hdead;
adc_data_1101[15: 0] <= 16'hdead;
adc_data_1011[63:48] <= 16'hdead;
adc_data_1011[47:32] <= 16'hdead;
adc_data_1011[31:16] <= 16'hdead;
adc_data_1011[15: 0] <= 16'hdead;
adc_data_0111[63:48] <= 16'hdead;
adc_data_0111[47:32] <= 16'hdead;
adc_data_0111[31:16] <= 16'hdead;
adc_data_0111[15: 0] <= 16'hdead;
end
always @(chan_data_0, chan_data_1, chan_data_2, chan_data_3, chan_enable_0, chan_enable_1, chan_enable_2, chan_enable_3, chan_valid)
begin
if(chan_valid == 1'b1)
begin
casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'bxxx1: temp_data_0[15:0] = chan_data_0;
4'bxx10: temp_data_0[15:0] = chan_data_1;
4'bx100: temp_data_0[15:0] = chan_data_2;
4'b1000: temp_data_0[15:0] = chan_data_3;
default: temp_data_0 [15:0] = 16'h0000;
endcase
casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'bxx11: temp_data_0[31:16] = chan_data_1;
4'bx110: temp_data_0[31:16] = chan_data_2;
4'bx101: temp_data_0[31:16] = chan_data_2;
4'b1001: temp_data_0[31:16] = chan_data_3;
4'b1010: temp_data_0[31:16] = chan_data_3;
4'b1100: temp_data_0[31:16] = chan_data_3;
default: temp_data_0[31:16] = 16'h0000;
endcase
casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'bx111: temp_data_0[47:32] = chan_data_2;
4'b1011: temp_data_0[47:32] = chan_data_3;
4'b1101: temp_data_0[47:32] = chan_data_3;
4'b1110: temp_data_0[47:32] = chan_data_3;
default: temp_data_0[47:32] = 16'h0000;
endcase
end
end
always @(posedge clk) begin
if (valid == 1'b1) begin
case ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
4'b1111: begin
adc_iqcor_valid <= 1'b1;
adc_iqcor_sync <= 1'b1;
adc_data[63:48] <= chan_data_3;
adc_data[47:32] <= chan_data_2;
adc_data[31:16] <= chan_data_1;
adc_data[15: 0] <= chan_data_0;
4'b1111: temp_data_0[63:48] = chan_data_3;
default: temp_data_0[63:48] = 16'h0000;
endcase
end
4'b1110: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_data <= adc_data_1110;
else
begin
temp_data_0 = 64'h0;
end
4'b1101: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_data <= adc_data_1101;
end
4'b1100: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_3;
adc_data[47:32] <= chan_data_2;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
always @(chan_data_4, chan_data_5, chan_data_6, chan_data_7, chan_enable_4, chan_enable_5, chan_enable_6, chan_enable_7, chan_valid)
begin
if(chan_valid == 1'b1)
begin
casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
4'bxxx1: temp_data_1[15:0] = chan_data_4;
4'bxx10: temp_data_1[15:0] = chan_data_5;
4'bx100: temp_data_1[15:0] = chan_data_6;
4'b1000: temp_data_1[15:0] = chan_data_7;
default: temp_data_1 [15:0] = 16'h0000;
endcase
casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
4'bxx11: temp_data_1[31:16] = chan_data_5;
4'bx110: temp_data_1[31:16] = chan_data_6;
4'bx101: temp_data_1[31:16] = chan_data_6;
4'b1001: temp_data_1[31:16] = chan_data_7;
4'b1010: temp_data_1[31:16] = chan_data_7;
4'b1100: temp_data_1[31:16] = chan_data_7;
default: temp_data_1[31:16] = 16'h0000;
endcase
casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
4'bx111: temp_data_1[47:32] = chan_data_6;
4'b1011: temp_data_1[47:32] = chan_data_7;
4'b1101: temp_data_1[47:32] = chan_data_7;
4'b1110: temp_data_1[47:32] = chan_data_7;
default: temp_data_1[47:32] = 16'h0000;
endcase
case ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
4'b1111: temp_data_1[63:48] = chan_data_7;
default: temp_data_1[63:48] = 16'h0000;
endcase
end
4'b1011: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_data <= adc_data_1011;
else
begin
temp_data_1 = 64'h0;
end
4'b1010: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_3;
adc_data[47:32] <= chan_data_1;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b1001: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_3;
adc_data[47:32] <= chan_data_0;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
always @(temp_data_0, temp_data_1, enable_cnt_0)
begin
packed_data = temp_data_0 | temp_data_1 << enable_cnt_0 * 16;
end
4'b1000: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= chan_data_3;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
always @(enable_cnt)
begin
case(enable_cnt)
4'h1: path_enabled = 8'h01;
4'h2: path_enabled = 8'h02;
4'h4: path_enabled = 8'h08;
4'h8: path_enabled = 8'h80;
default: path_enabled = 8'h0;
endcase
end
4'b0111: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_data <= adc_data_0111;
always @(posedge clk)
begin
if (path_enabled == 8'h0)
begin
counter_0 <= 7'h0;
end
4'b0110: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_2;
adc_data[47:32] <= chan_data_1;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
else
begin
if( chan_valid == 1'b1)
begin
if (counter_0 > 7)
begin
counter_0 <= counter_0 - 8 + enable_cnt;
end
4'b0101: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_2;
adc_data[47:32] <= chan_data_0;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
else
begin
counter_0 <= counter_0 + enable_cnt;
end
4'b0100: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= chan_data_2;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
if ((counter_0 == (8 - enable_cnt)) || (path_enabled == 8'h80) )
begin
dvalid <= 1'b1;
end
4'b0011: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_1;
adc_data[47:32] <= chan_data_0;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
else
begin
dvalid <= 1'b0;
end
4'b0010: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= chan_data_1;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
4'b0001: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= chan_data_0;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
else
begin
dvalid <= 1'b0;
end
default: begin
adc_iqcor_valid <= 1'b1;
adc_data[63:48] <= 16'hdead;
adc_data[47:32] <= 16'hdead;
adc_data[31:16] <= 16'hdead;
adc_data[15: 0] <= 16'hdead;
end
end
always @(counter_0, path_enabled)
begin
case (counter_0)
0:
begin
en1 = path_enabled[0];
en2 = {2{path_enabled[1]}};
en4 = {4{path_enabled[3]}};
end
1:
begin
en1 = path_enabled[0] << 1;
en2 = {2{path_enabled[1]}} << 0;
en4 = {4{path_enabled[3]}} << 0;
end
2:
begin
en1 = path_enabled[0] << 2;
en2 = {2{path_enabled[1]}} << 2;
en4 = {4{path_enabled[3]}} << 0;
end
3:
begin
en1 = path_enabled[0] << 3;
en2 = {2{path_enabled[1]}} << 2;
en4 = {4{path_enabled[3]}} << 0;
end
4:
begin
en1 = path_enabled[0] << 4;
en2 = {2{path_enabled[1]}} << 4;
en4 = {4{path_enabled[3]}} << 4;
end
5:
begin
en1 = path_enabled[0] << 5;
en2 = {2{path_enabled[1]}} << 4;
en4 = {4{path_enabled[3]}} << 4;
end
6:
begin
en1 = path_enabled[0] << 6;
en2 = {2{path_enabled[1]}} << 6;
en4 = {4{path_enabled[3]}} << 4;
end
7:
begin
en1 = path_enabled[0] << 7;
en2 = {2{path_enabled[1]}} << 6;
en4 = {4{path_enabled[3]}} << 4;
end
8:
begin
en1 = path_enabled[0] << 0;
en2 = {2{path_enabled[1]}} << 0;
en4 = {4{path_enabled[3]}} << 0;
end
default:
begin
en1 = 8'h0;
en2 = 8'h0;
en4 = 8'h0;
end
endcase
adc_data_cnt <= adc_data_cnt + 1'b1;
end else begin
adc_iqcor_valid <= 1'b0;
adc_data <= adc_data;
adc_data_cnt <= adc_data_cnt;
end
always @(posedge clk)
begin
// ddata[15:0]
if ((en1[0] | en2[0] | en4[0] | path_enabled[7]) == 1'b1)
begin
ddata[15:0] <= packed_data[15:0];
end
// ddata[31:16]
if( en1[1] == 1'b1)
begin
ddata[31:16] <= packed_data[15:0];
end
if ( (en2[1] | en4[1] | path_enabled[7]) == 1'b1)
begin
ddata[31:16] <= packed_data[31:16];
end
// ddata[47:32]
if ((en1[2] | en2[2]) == 1'b1)
begin
ddata[47:32] <= packed_data[15:0];
end
if ((en4[2] | path_enabled[7]) == 1'b1)
begin
ddata[47:32] <= packed_data[47:32];
end
// ddata[63:48]
if (en1[3] == 1'b1)
begin
ddata[63:48] <= packed_data[15:0];
end
if (en2[3] == 1'b1)
begin
ddata[63:48] <= packed_data[31:16];
end
if ((en4[3] | path_enabled[7]) == 1'b1)
begin
ddata[63:48] <= packed_data[63:48];
end
// ddata[79:64]
if ((en1[4] | en2[4] | en4[4]) == 1'b1)
begin
ddata[79:64] <= packed_data[15:0];
end
if (path_enabled[7] == 1'b1)
begin
ddata[79:64] <= packed_data[79:64];
end
// ddata[95:80]
if (en1[5] == 1'b1)
begin
ddata[95:80] <= packed_data[15:0];
end
if ((en2[5] | en4[5]) == 1'b1)
begin
ddata[95:80] <= packed_data[31:16];
end
if (path_enabled[7] == 1'b1)
begin
ddata[95:80] <= packed_data[95:80];
end
// ddata[111:96]
if ((en1[6] | en2[6]) == 1'b1)
begin
ddata[111:96] <= packed_data[15:0];
end
if (en4[6] == 1'b1)
begin
ddata[111:96] <= packed_data[47:32];
end
if (path_enabled[7] == 1'b1)
begin
ddata[111:96] <= packed_data[111:96];
end
// ddata[127:112]
if (en1[7] == 1'b1)
begin
ddata[127:112] <= packed_data[15:0];
end
if (en2[7] == 1'b1)
begin
ddata[127:112] <= packed_data[31:16];
end
if (en4[7] == 1'b1)
begin
ddata[127:112] <= packed_data[63:48];
end
if (path_enabled[7] == 1'b1)
begin
ddata[127:112] <= packed_data[127:112];
end
end
endmodule

753
library/util_dac_unpack/util_dac_unpack.v
View File

@ -41,6 +41,8 @@
module util_dac_unpack (
clk,
dac_enable_00,
dac_valid_00,
dac_data_00,
@ -57,9 +59,28 @@ module util_dac_unpack (
dac_valid_03,
dac_data_03,
dac_enable_04,
dac_valid_04,
dac_data_04,
dac_enable_05,
dac_valid_05,
dac_data_05,
dac_enable_06,
dac_valid_06,
dac_data_06,
dac_enable_07,
dac_valid_07,
dac_data_07,
fifo_valid,
dma_rd,
dma_data);
input clk;
input dac_enable_00;
input dac_valid_00;
output [ 15:0] dac_data_00;
@ -76,14 +97,732 @@ module util_dac_unpack (
input dac_valid_03;
output [ 15:0] dac_data_03;
output dma_rd;
input [ 63:0] dma_data;
input dac_enable_04;
input dac_valid_04;
output [ 15:0] dac_data_04;
assign dma_rd = dac_valid_00 | dac_valid_01 | dac_valid_02 | dac_valid_03;
assign dac_data_00 = dma_data[15: 0];
assign dac_data_01 = dma_data[31:16];
assign dac_data_02 = dma_data[47:32];
assign dac_data_03 = dma_data[63:48];
input dac_enable_05;
input dac_valid_05;
output [ 15:0] dac_data_05;
input dac_enable_06;
input dac_valid_06;
output [ 15:0] dac_data_06;
input dac_enable_07;
input dac_valid_07;
output [ 15:0] dac_data_07;
input fifo_valid;
output dma_rd;
input [127:0] dma_data;
wire [3:0] enable_cnt;
wire dac_chan_valid;
wire [ 1:0] position_2;
wire [ 1:0] position_3;
wire [ 2:0] position_4;
wire [ 2:0] position_5;
wire [ 2:0] position_6;
wire [ 2:0] position_7;
reg [ 7:0] path_enabled = 0;
reg [ 2:0] counter_0 = 0;
reg [ 2:0] counter_d1 = 0;
reg [ 15:0] dac_data_00 = 16'h0;
reg [ 15:0] dac_data_01 = 16'h0;
reg [ 15:0] dac_data_02 = 16'h0;
reg [ 15:0] dac_data_03 = 16'h0;
reg [ 15:0] dac_data_04 = 16'h0;
reg [ 15:0] dac_data_05 = 16'h0;
reg [ 15:0] dac_data_06 = 16'h0;
reg [ 15:0] dac_data_07 = 16'h0;
reg [127:0] buffer_r = 128'h0;
reg dma_rd = 1'b0;
reg start = 1'b0;
assign enable_cnt = dac_enable_07 + dac_enable_06 + dac_enable_05 + dac_enable_04 + dac_enable_03 + dac_enable_02 + dac_enable_01 + dac_enable_00;
assign position_2 = dac_enable_00 + dac_enable_01;
assign position_3 = dac_enable_00 + dac_enable_01 + dac_enable_02;
assign position_4 = dac_enable_00 + dac_enable_01 + dac_enable_02 + dac_enable_03;
assign position_5 = dac_enable_00 + dac_enable_01 + dac_enable_02 + dac_enable_03 + dac_enable_04;
assign position_6 = dac_enable_00 + dac_enable_01 + dac_enable_02 + dac_enable_03 + dac_enable_04 + dac_enable_05;
assign position_7 = dac_enable_00 + dac_enable_01 + dac_enable_02 + dac_enable_03 + dac_enable_04 + dac_enable_05 + dac_enable_06;
assign dac_chan_valid = dac_valid_07 | dac_valid_06 | dac_valid_05 | dac_valid_04 | dac_valid_03 | dac_valid_02 | dac_valid_01 | dac_valid_00;
always @(enable_cnt)
begin
case(enable_cnt)
4'h1: path_enabled = 8'h01;
4'h2: path_enabled = 8'h02;
4'h4: path_enabled = 8'h08;
4'h8: path_enabled = 8'h80;
default: path_enabled = 8'h0;
endcase
end
always @(posedge clk)
begin
counter_d1 <= counter_0;
case (path_enabled)
8'h1:
begin
if (counter_0 == 7 && counter_d1 == 6)
begin
dma_rd <= 1'b1;
end
else
begin
dma_rd <= 1'b0;
end
end
8'h02:
begin
if(counter_0 == 6 && counter_d1 == 4)
begin
dma_rd <= 1'b1;
end
else
begin
dma_rd <= 1'b0;
end
end
8'h08:
begin
if(counter_0 == 4 && counter_d1 == 0)
begin
dma_rd <= 1'b1;
end
else
begin
dma_rd <= 1'b0;
end
end
8'h80:
begin
dma_rd <= 1'b1;
end
default : dma_rd <= 1'b0;
endcase
if (fifo_valid == 1'b1)
begin
buffer_r <= dma_data;
end
end
always @(posedge clk)
begin
if (path_enabled == 8'h0)
begin
counter_0 <= 3'h0;
end
else
begin
if (dac_chan_valid == 1'b1 )
begin
counter_0 <= counter_0 + enable_cnt;
end
end
end
always @(posedge clk)
begin
// channel 0
if (dac_enable_00 == 1'b1)
begin
case(counter_0)
0:
begin
dac_data_00 <= buffer_r[15:0];
end
1:
begin
dac_data_00 <= buffer_r[31:16];
end
2:
begin
dac_data_00 <= buffer_r[47:32];
end
3:
begin
dac_data_00 <= buffer_r [63:48];
end
4:
begin
dac_data_00 <= buffer_r [79:64];
end
5:
begin
dac_data_00 <= buffer_r [95:80];
end
6:
begin
dac_data_00 <= buffer_r [111:96];
end
7:
begin
dac_data_00 <= buffer_r [127:112];
end
default:
begin
dac_data_00 <= 16'hdead;
end
endcase
end
else
begin
dac_data_00 <= 16'h0;
end
// channel 1
if (dac_enable_01 == 1'b1)
begin
case (counter_0)
0:
begin
if (dac_enable_00 == 1'b0)
begin
dac_data_01 <= buffer_r[15:0];
end
else
begin
dac_data_01 <= buffer_r[31:16];
end
end
1:
begin
dac_data_01 <= buffer_r[31:16];
end
2:
begin
if (dac_enable_00 == 1'b0 )
begin
dac_data_01 <= buffer_r[47:32];
end
else
begin
dac_data_01 <= buffer_r[63:48];
end
end
3:
begin
dac_data_01 <= buffer_r[63:48];
end
4:
begin
begin
if (dac_enable_00 == 1'b0)
begin
dac_data_01 <= buffer_r[79:64];
end
else
begin
dac_data_01 <= buffer_r[95:80];
end
end
end
5:
begin
dac_data_01 <= buffer_r[95:80];
end
6:
begin
if (path_enabled == 8'h1)
begin
dac_data_01 <= buffer_r [111:96];
end
if (path_enabled == 8'h2)
begin
if (dac_enable_00 == 1'b0)
begin
dac_data_01 <= buffer_r[111:96];
end
else
begin
dac_data_01 <= buffer_r[127:112];
end
end
end
7:
begin
dac_data_01 <= buffer_r[127:112];
end
default:
begin
dac_data_01 <= 16'hdead;
end
endcase
end
else
begin
dac_data_01 <= 16'h0;
end
// channel 2
if (dac_enable_02 == 1'b1)
begin
case (counter_0)
0:
begin
if (position_2 == 2'h00)
begin
dac_data_02 <= buffer_r[15:0];
end
if (position_2 == 2'h01)
begin
dac_data_02 <= buffer_r[31:16];
end
if (position_2 == 2'h02)
begin
dac_data_02 <= buffer_r[47:32];
end
end
1:
begin
dac_data_02 <= buffer_r[31:16];
end
2:
begin
if (position_2 == 2'h00)
begin
dac_data_02 <= buffer_r[47:32];
end
else
begin
dac_data_02 <= buffer_r[63:48];
end
end
3:
begin
dac_data_02 <= buffer_r[63:48];
end
4:
begin
if (position_2 == 2'h00)
begin
dac_data_02 <= buffer_r[79:64];
end
if (position_2 == 2'h01)
begin
dac_data_02 <= buffer_r[95:80];
end
if (position_2 == 2'h02)
begin
dac_data_02 <= buffer_r[111:96];
end
end
5:
begin
dac_data_02 <= buffer_r[95:80];
end
6:
begin
if (position_2 == 2'h00)
begin
dac_data_02 <= buffer_r[111:96];
end
else
begin
dac_data_02 <= buffer_r[127:112];
end
end
7:
begin
dac_data_02 <= buffer_r[127:112];
end
default:
begin
dac_data_02 <= 16'hdead;
end
endcase
end
else
begin
dac_data_02 <= 16'h0;
end
// channel 3
if (dac_enable_03 == 1'b1)
begin
case (counter_0)
0:
begin
if (position_3 == 2'h00)
begin
dac_data_03 <= buffer_r [15:0];
end
if (position_3 == 2'h01)
begin
dac_data_03 <= buffer_r [31:16];
end
if (position_3 == 2'h02)
begin
dac_data_03 <= buffer_r [47:32];
end
if (position_3 == 2'h03)
begin
dac_data_03 <= buffer_r [63:48];
end
end
1:
begin
dac_data_03 <= buffer_r [31:16];
end
2:
begin
if (position_3 == 2'h00)
begin
dac_data_03 <= buffer_r [47:32];
end
else
begin
dac_data_03 <= buffer_r [63:48];
end
end
3:
begin
dac_data_03 <= buffer_r [63:48];
end
4:
begin
if (position_3 == 2'h00)
begin
dac_data_03 <= buffer_r [79:64];
end
if (position_3 == 2'h01)
begin
dac_data_03 <= buffer_r [95:80];
end
if (position_3 == 2'h02)
begin
dac_data_03 <= buffer_r [111:96];
end
if (position_3 == 2'h03)
begin
dac_data_03 <= buffer_r [127:112];
end
end
5:
begin
dac_data_03 <= buffer_r [95:80];
end
6:
begin
if (position_3 == 2'h00)
begin
dac_data_03 <= buffer_r [111:96];
end
else
begin
dac_data_03 <= buffer_r [127:112];
end
end
7:
begin
dac_data_03 <= buffer_r [127:112];
end
default:
begin
dac_data_03 <= 16'hdead;
end
endcase
end
else
begin
dac_data_03 <= 16'h0;
end
// channel 4
if (dac_enable_04 == 1'b1)
begin
case (counter_0)
0:
begin
case (position_4)
0: dac_data_04 <= buffer_r [15:0];
1: dac_data_04 <= buffer_r [31:16];
2: dac_data_04 <= buffer_r [47:32];
3: dac_data_04 <= buffer_r [63:48];
default: dac_data_04 <= buffer_r[79:64];
endcase
end
1:
begin
dac_data_04 <= buffer_r [31:16];
end
2:
begin
if (position_4 == 3'h00)
begin
dac_data_04 <= buffer_r [47:32];
end
else
begin
dac_data_04 <= buffer_r [63:48];
end
end
3:
begin
dac_data_04 <= buffer_r [63:48];
end
4:
begin
case (position_4)
0: dac_data_04 <= buffer_r [79:64];
1: dac_data_04 <= buffer_r [95:80];
2: dac_data_04 <= buffer_r [111:96];
default: dac_data_04 <= buffer_r [127:112];
endcase
end
5:
begin
dac_data_04 <= buffer_r [95:80];
end
6:
begin
if (position_4 == 2'h00)
begin
dac_data_04 <= buffer_r [111:96];
end
else
begin
dac_data_04 <= buffer_r [127:112];
end
end
7:
begin
dac_data_04 <= buffer_r [127:112];
end
default:
begin
dac_data_04 <= 16'hdead;
end
endcase
end
else
begin
dac_data_04 <= 16'h0;
end
// channel 5
if (dac_enable_05 == 1'b1)
begin
case (counter_0)
0:
begin
case (position_5)
0: dac_data_05 <= buffer_r [15:0];
1: dac_data_05 <= buffer_r [31:16];
2: dac_data_05 <= buffer_r [47:32];
3: dac_data_05 <= buffer_r [63:48];
default: dac_data_05 <= buffer_r[95:80];
endcase
end
1:
begin
dac_data_05 <= buffer_r [31:16];
end
2:
begin
if (position_5 == 3'h00)
begin
dac_data_05 <= buffer_r [47:32];
end
else
begin
dac_data_05 <= buffer_r [63:48];
end
end
3:
begin
dac_data_05 <= buffer_r [63:48];
end
4:
begin
case (position_5)
0: dac_data_05 <= buffer_r [79:64];
1: dac_data_05 <= buffer_r [95:80];
2: dac_data_05 <= buffer_r [111:96];
default: dac_data_05 <= buffer_r [127:112];
endcase
end
5:
begin
dac_data_05 <= buffer_r [95:80];
end
6:
begin
if (position_5 == 2'h00)
begin
dac_data_05 <= buffer_r [111:96];
end
else
begin
dac_data_05 <= buffer_r [127:112];
end
end
7:
begin
dac_data_05 <= buffer_r [127:112];
end
default:
begin
dac_data_05 <= 16'hdead;
end
endcase
end
else
begin
dac_data_05 <= 16'h0;
end
// channel 6
if (dac_enable_06 == 1'b1)
begin
case (counter_0)
0:
begin
case (position_6)
0: dac_data_06 <= buffer_r [15:0];
1: dac_data_06 <= buffer_r [31:16];
2: dac_data_06 <= buffer_r [47:32];
3: dac_data_06 <= buffer_r [63:48];
default: dac_data_06 <= buffer_r[111:96];
endcase
end
1:
begin
dac_data_06 <= buffer_r [31:16];
end
2:
begin
if (position_6 == 3'h00)
begin
dac_data_06 <= buffer_r [47:32];
end
else
begin
dac_data_06 <= buffer_r [63:48];
end
end
3:
begin
dac_data_06 <= buffer_r [63:48];
end
4:
begin
case (position_6)
0: dac_data_06 <= buffer_r [79:64];
1: dac_data_06 <= buffer_r [95:80];
2: dac_data_06 <= buffer_r [111:96];
default: dac_data_06 <= buffer_r [127:112];
endcase
end
5:
begin
dac_data_06 <= buffer_r [95:80];
end
6:
begin
if (position_6 == 2'h00)
begin
dac_data_06 <= buffer_r [111:96];
end
else
begin
dac_data_06 <= buffer_r [127:112];
end
end
7:
begin
dac_data_06 <= buffer_r [127:112];
end
default:
begin
dac_data_06 <= 16'hdead;
end
endcase
end
else
begin
dac_data_06 <= 16'h0;
end
// channel 7
if (dac_enable_07 == 1'b1)
begin
case (counter_0)
0:
begin
case (position_7)
0: dac_data_07 <= buffer_r[15:0];
1: dac_data_07 <= buffer_r[31:16];
3: dac_data_07 <= buffer_r[63:48];
default: dac_data_07 <= buffer_r[127:112];
endcase
end
1:
begin
dac_data_07 <= buffer_r [31:16];
end
2:
begin
if (position_7 == 3'h00)
begin
dac_data_07 <= buffer_r [47:32];
end
else
begin
dac_data_07 <= buffer_r [63:48];
end
end
3:
begin
dac_data_07 <= buffer_r [63:48];
end
4:
begin
case (position_7)
0: dac_data_07 <= buffer_r [79:64];
1: dac_data_07 <= buffer_r [95:80];
default: dac_data_07 <= buffer_r [127:112];
endcase
end
5:
begin
dac_data_07 <= buffer_r [95:80];
end
6:
begin
if (position_7 == 2'h00)
begin
dac_data_07 <= buffer_r [111:96];
end
else
begin
dac_data_07 <= buffer_r [127:112];
end
end
7:
begin
dac_data_07 <= buffer_r [127:112];
end
default:
begin
dac_data_07 <= 16'hdead;
end
endcase
end
else
begin
dac_data_07 <= 16'h0;
end
end
endmodule

25
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -45,12 +45,17 @@
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_dac_dma
# channel packing for the ADC
set util_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack]
set util_dac_unpack [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack]
# constant 0
set constant_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 constant_0]
set_property -dict [list CONFIG.CONST_VAL {0}] $constant_0
if {$sys_zynq == 1} {
set axi_ad9361_dac_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_dac_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9361_dac_dma_interconnect
@ -67,6 +72,7 @@ if {$sys_zynq == 1} {
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma
if {$sys_zynq == 1} {
set axi_ad9361_adc_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_adc_dma_interconnect]
@ -167,6 +173,14 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9361_tx_data_out_n [get_bd_ports tx_data_out_n] [get_bd_pins axi_ad9361/tx_data_out_n]
connect_bd_net -net axi_ad9361_clk [get_bd_pins util_adc_pack/clk]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_valid_4]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_valid_5]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_valid_6]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_valid_7]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_enable_4]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_enable_5]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_enable_6]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_enable_7]
connect_bd_net -net axi_ad9361_adc_valid_0 [get_bd_pins axi_ad9361/adc_valid_i0] [get_bd_pins util_adc_pack/chan_valid_0]
connect_bd_net -net axi_ad9361_adc_valid_1 [get_bd_pins axi_ad9361/adc_valid_q0] [get_bd_pins util_adc_pack/chan_valid_1]
connect_bd_net -net axi_ad9361_adc_valid_2 [get_bd_pins axi_ad9361/adc_valid_i1] [get_bd_pins util_adc_pack/chan_valid_2]
@ -184,20 +198,30 @@ if {$sys_zynq == 0} {
connect_bd_net -net util_adc_pack_ddata [get_bd_pins util_adc_pack/ddata] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din]
connect_bd_net -net axi_ad9361_adc_dovf [get_bd_pins axi_ad9361/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9361_clk [get_bd_pins util_dac_unpack/clk]
connect_bd_net -net axi_ad9361_dac_valid_0 [get_bd_pins util_dac_unpack/dac_valid_00] [get_bd_pins axi_ad9361/dac_valid_i0]
connect_bd_net -net axi_ad9361_dac_valid_1 [get_bd_pins util_dac_unpack/dac_valid_01] [get_bd_pins axi_ad9361/dac_valid_q0]
connect_bd_net -net axi_ad9361_dac_valid_2 [get_bd_pins util_dac_unpack/dac_valid_02] [get_bd_pins axi_ad9361/dac_valid_i1]
connect_bd_net -net axi_ad9361_dac_valid_3 [get_bd_pins util_dac_unpack/dac_valid_03] [get_bd_pins axi_ad9361/dac_valid_q1]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_valid_04]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_valid_05]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_valid_06]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_valid_07]
connect_bd_net -net axi_ad9361_dac_enable_0 [get_bd_pins util_dac_unpack/dac_enable_00] [get_bd_pins axi_ad9361/dac_enable_i0]
connect_bd_net -net axi_ad9361_dac_enable_1 [get_bd_pins util_dac_unpack/dac_enable_01] [get_bd_pins axi_ad9361/dac_enable_q0]
connect_bd_net -net axi_ad9361_dac_enable_2 [get_bd_pins util_dac_unpack/dac_enable_02] [get_bd_pins axi_ad9361/dac_enable_i1]
connect_bd_net -net axi_ad9361_dac_enable_3 [get_bd_pins util_dac_unpack/dac_enable_03] [get_bd_pins axi_ad9361/dac_enable_q1]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_enable_04]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_enable_05]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_enable_06]
connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_enable_07]
connect_bd_net -net axi_ad9361_dac_data_0 [get_bd_pins util_dac_unpack/dac_data_00] [get_bd_pins axi_ad9361/dac_data_i0]
connect_bd_net -net axi_ad9361_dac_data_1 [get_bd_pins util_dac_unpack/dac_data_01] [get_bd_pins axi_ad9361/dac_data_q0]
connect_bd_net -net axi_ad9361_dac_data_2 [get_bd_pins util_dac_unpack/dac_data_02] [get_bd_pins axi_ad9361/dac_data_i1]
connect_bd_net -net axi_ad9361_dac_data_3 [get_bd_pins util_dac_unpack/dac_data_03] [get_bd_pins axi_ad9361/dac_data_q1]
connect_bd_net -net fifo_data [get_bd_pins util_dac_unpack/dma_data] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout]
connect_bd_net -net fifo_valid [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] [get_bd_pins util_dac_unpack/fifo_valid]
connect_bd_net -net axi_ad9361_dac_drd [get_bd_pins util_dac_unpack/dma_rd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en]
connect_bd_net -net axi_ad9361_dac_dunf [get_bd_pins axi_ad9361/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow]
@ -299,6 +323,7 @@ if {$sys_zynq == 0} {
set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE4_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
connect_bd_net -net axi_ad9361_clk [get_bd_pins ila_adc/clk]
connect_bd_net -net axi_ad9361_adc_valid_0 [get_bd_pins ila_adc/probe0]

75
projects/fmcomms5/common/fmcomms5_bd.tcl
View File

@ -31,16 +31,6 @@ set tx_frame_out_1_n [create_bd_port -dir O tx_frame_out_1_n]
set tx_data_out_1_p [create_bd_port -dir O -from 5 -to 0 tx_data_out_1_p]
set tx_data_out_1_n [create_bd_port -dir O -from 5 -to 0 tx_data_out_1_n]
# dma multiplexing
set ad9361_0_dac_ddata [create_bd_port -dir I -from 63 -to 0 ad9361_0_dac_ddata]
set ad9361_1_dac_ddata [create_bd_port -dir I -from 63 -to 0 ad9361_1_dac_ddata]
set ad9361_dac_ddata [create_bd_port -dir O -from 127 -to 0 ad9361_dac_ddata]
set ad9361_0_adc_ddata [create_bd_port -dir O -from 63 -to 0 ad9361_0_adc_ddata]
set ad9361_1_adc_ddata [create_bd_port -dir O -from 63 -to 0 ad9361_1_adc_ddata]
set ad9361_adc_ddata [create_bd_port -dir I -from 127 -to 0 ad9361_adc_ddata]
set sys_100m_resetn [create_bd_port -dir O sys_100m_resetn]
set sys_100m_clk [create_bd_port -dir O sys_100m_clk]
@ -130,8 +120,6 @@ if {$sys_zynq == 0} {
set util_adc_pack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack_0]
set util_dac_unpack_0 [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack_0]
set util_adc_pack_1 [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack_1]
set util_dac_unpack_1 [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack_1]
# additions to default configuration
@ -202,7 +190,7 @@ connect_bd_net -net axi_ad9361_1_clk [get_bd_pins axi_ad9361_1/l_clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_0/clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_1/clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins util_adc_pack_0/clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins util_adc_pack_1/clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins util_dac_unpack_0/clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_adc_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins axi_ad9361_dac_dma/fifo_rd_clk]
@ -246,23 +234,21 @@ connect_bd_net -net axi_ad9361_0_adc_data_i1 [get_bd_pins axi_ad9361_0/adc_
connect_bd_net -net axi_ad9361_0_adc_enable_q1 [get_bd_pins axi_ad9361_0/adc_enable_q1] [get_bd_pins util_adc_pack_0/chan_enable_3]
connect_bd_net -net axi_ad9361_0_adc_valid_q1 [get_bd_pins axi_ad9361_0/adc_valid_q1] [get_bd_pins util_adc_pack_0/chan_valid_3]
connect_bd_net -net axi_ad9361_0_adc_data_q1 [get_bd_pins axi_ad9361_0/adc_data_q1] [get_bd_pins util_adc_pack_0/chan_data_3]
connect_bd_net -net axi_ad9361_1_adc_enable_i0 [get_bd_pins axi_ad9361_1/adc_enable_i0] [get_bd_pins util_adc_pack_1/chan_enable_0]
connect_bd_net -net axi_ad9361_1_adc_valid_i0 [get_bd_pins axi_ad9361_1/adc_valid_i0] [get_bd_pins util_adc_pack_1/chan_valid_0]
connect_bd_net -net axi_ad9361_1_adc_data_i0 [get_bd_pins axi_ad9361_1/adc_data_i0] [get_bd_pins util_adc_pack_1/chan_data_0]
connect_bd_net -net axi_ad9361_1_adc_enable_q0 [get_bd_pins axi_ad9361_1/adc_enable_q0] [get_bd_pins util_adc_pack_1/chan_enable_1]
connect_bd_net -net axi_ad9361_1_adc_valid_q0 [get_bd_pins axi_ad9361_1/adc_valid_q0] [get_bd_pins util_adc_pack_1/chan_valid_1]
connect_bd_net -net axi_ad9361_1_adc_data_q0 [get_bd_pins axi_ad9361_1/adc_data_q0] [get_bd_pins util_adc_pack_1/chan_data_1]
connect_bd_net -net axi_ad9361_1_adc_enable_i1 [get_bd_pins axi_ad9361_1/adc_enable_i1] [get_bd_pins util_adc_pack_1/chan_enable_2]
connect_bd_net -net axi_ad9361_1_adc_valid_i1 [get_bd_pins axi_ad9361_1/adc_valid_i1] [get_bd_pins util_adc_pack_1/chan_valid_2]
connect_bd_net -net axi_ad9361_1_adc_data_i1 [get_bd_pins axi_ad9361_1/adc_data_i1] [get_bd_pins util_adc_pack_1/chan_data_2]
connect_bd_net -net axi_ad9361_1_adc_enable_q1 [get_bd_pins axi_ad9361_1/adc_enable_q1] [get_bd_pins util_adc_pack_1/chan_enable_3]
connect_bd_net -net axi_ad9361_1_adc_valid_q1 [get_bd_pins axi_ad9361_1/adc_valid_q1] [get_bd_pins util_adc_pack_1/chan_valid_3]
connect_bd_net -net axi_ad9361_1_adc_data_q1 [get_bd_pins axi_ad9361_1/adc_data_q1] [get_bd_pins util_adc_pack_1/chan_data_3]
connect_bd_net -net axi_ad9361_1_adc_enable_i0 [get_bd_pins axi_ad9361_1/adc_enable_i0] [get_bd_pins util_adc_pack_0/chan_enable_4]
connect_bd_net -net axi_ad9361_1_adc_valid_i0 [get_bd_pins axi_ad9361_1/adc_valid_i0] [get_bd_pins util_adc_pack_0/chan_valid_4]
connect_bd_net -net axi_ad9361_1_adc_data_i0 [get_bd_pins axi_ad9361_1/adc_data_i0] [get_bd_pins util_adc_pack_0/chan_data_4]
connect_bd_net -net axi_ad9361_1_adc_enable_q0 [get_bd_pins axi_ad9361_1/adc_enable_q0] [get_bd_pins util_adc_pack_0/chan_enable_5]
connect_bd_net -net axi_ad9361_1_adc_valid_q0 [get_bd_pins axi_ad9361_1/adc_valid_q0] [get_bd_pins util_adc_pack_0/chan_valid_5]
connect_bd_net -net axi_ad9361_1_adc_data_q0 [get_bd_pins axi_ad9361_1/adc_data_q0] [get_bd_pins util_adc_pack_0/chan_data_5]
connect_bd_net -net axi_ad9361_1_adc_enable_i1 [get_bd_pins axi_ad9361_1/adc_enable_i1] [get_bd_pins util_adc_pack_0/chan_enable_6]
connect_bd_net -net axi_ad9361_1_adc_valid_i1 [get_bd_pins axi_ad9361_1/adc_valid_i1] [get_bd_pins util_adc_pack_0/chan_valid_6]
connect_bd_net -net axi_ad9361_1_adc_data_i1 [get_bd_pins axi_ad9361_1/adc_data_i1] [get_bd_pins util_adc_pack_0/chan_data_6]
connect_bd_net -net axi_ad9361_1_adc_enable_q1 [get_bd_pins axi_ad9361_1/adc_enable_q1] [get_bd_pins util_adc_pack_0/chan_enable_7]
connect_bd_net -net axi_ad9361_1_adc_valid_q1 [get_bd_pins axi_ad9361_1/adc_valid_q1] [get_bd_pins util_adc_pack_0/chan_valid_7]
connect_bd_net -net axi_ad9361_1_adc_data_q1 [get_bd_pins axi_ad9361_1/adc_data_q1] [get_bd_pins util_adc_pack_0/chan_data_7]
connect_bd_net -net axi_ad9361_0_dvalid [get_bd_pins util_adc_pack_0/dvalid] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en]
connect_bd_net -net axi_ad9361_0_dsync [get_bd_pins util_adc_pack_0/dsync] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9361_0_adc_ddata [get_bd_pins util_adc_pack_0/ddata] [get_bd_ports ad9361_0_adc_ddata]
connect_bd_net -net axi_ad9361_1_adc_ddata [get_bd_pins util_adc_pack_1/ddata] [get_bd_ports ad9361_1_adc_ddata]
connect_bd_net -net axi_ad9361_adc_ddata [get_bd_ports ad9361_adc_ddata] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din]
connect_bd_net -net axi_ad9361_adc_ddata [get_bd_pins util_adc_pack_0/ddata] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din]
connect_bd_net -net axi_ad9361_0_dac_enable_0 [get_bd_pins axi_ad9361_0/dac_enable_i0] [get_bd_pins util_dac_unpack_0/dac_enable_00]
connect_bd_net -net axi_ad9361_0_dac_valid_0 [get_bd_pins axi_ad9361_0/dac_valid_i0] [get_bd_pins util_dac_unpack_0/dac_valid_00]
connect_bd_net -net axi_ad9361_0_dac_data_0 [get_bd_pins axi_ad9361_0/dac_data_i0] [get_bd_pins util_dac_unpack_0/dac_data_00]
@ -275,22 +261,21 @@ connect_bd_net -net axi_ad9361_0_dac_data_2 [get_bd_pins axi_ad9361_0/dac_
connect_bd_net -net axi_ad9361_0_dac_enable_3 [get_bd_pins axi_ad9361_0/dac_enable_q1] [get_bd_pins util_dac_unpack_0/dac_enable_03]
connect_bd_net -net axi_ad9361_0_dac_valid_3 [get_bd_pins axi_ad9361_0/dac_valid_q1] [get_bd_pins util_dac_unpack_0/dac_valid_03]
connect_bd_net -net axi_ad9361_0_dac_data_3 [get_bd_pins axi_ad9361_0/dac_data_q1] [get_bd_pins util_dac_unpack_0/dac_data_03]
connect_bd_net -net axi_ad9361_1_dac_enable_0 [get_bd_pins axi_ad9361_1/dac_enable_i0] [get_bd_pins util_dac_unpack_1/dac_enable_00]
connect_bd_net -net axi_ad9361_1_dac_valid_0 [get_bd_pins axi_ad9361_1/dac_valid_i0] [get_bd_pins util_dac_unpack_1/dac_valid_00]
connect_bd_net -net axi_ad9361_1_dac_data_0 [get_bd_pins axi_ad9361_1/dac_data_i0] [get_bd_pins util_dac_unpack_1/dac_data_00]
connect_bd_net -net axi_ad9361_1_dac_enable_1 [get_bd_pins axi_ad9361_1/dac_enable_q0] [get_bd_pins util_dac_unpack_1/dac_enable_01]
connect_bd_net -net axi_ad9361_1_dac_valid_1 [get_bd_pins axi_ad9361_1/dac_valid_q0] [get_bd_pins util_dac_unpack_1/dac_valid_01]
connect_bd_net -net axi_ad9361_1_dac_data_1 [get_bd_pins axi_ad9361_1/dac_data_q0] [get_bd_pins util_dac_unpack_1/dac_data_01]
connect_bd_net -net axi_ad9361_1_dac_enable_2 [get_bd_pins axi_ad9361_1/dac_enable_i1] [get_bd_pins util_dac_unpack_1/dac_enable_02]
connect_bd_net -net axi_ad9361_1_dac_valid_2 [get_bd_pins axi_ad9361_1/dac_valid_i1] [get_bd_pins util_dac_unpack_1/dac_valid_02]
connect_bd_net -net axi_ad9361_1_dac_data_2 [get_bd_pins axi_ad9361_1/dac_data_i1] [get_bd_pins util_dac_unpack_1/dac_data_02]
connect_bd_net -net axi_ad9361_1_dac_enable_3 [get_bd_pins axi_ad9361_1/dac_enable_q1] [get_bd_pins util_dac_unpack_1/dac_enable_03]
connect_bd_net -net axi_ad9361_1_dac_valid_3 [get_bd_pins axi_ad9361_1/dac_valid_q1] [get_bd_pins util_dac_unpack_1/dac_valid_03]
connect_bd_net -net axi_ad9361_1_dac_data_3 [get_bd_pins axi_ad9361_1/dac_data_q1] [get_bd_pins util_dac_unpack_1/dac_data_03]
connect_bd_net -net axi_ad9361_1_dac_enable_0 [get_bd_pins axi_ad9361_1/dac_enable_i0] [get_bd_pins util_dac_unpack_0/dac_enable_04]
connect_bd_net -net axi_ad9361_1_dac_valid_0 [get_bd_pins axi_ad9361_1/dac_valid_i0] [get_bd_pins util_dac_unpack_0/dac_valid_04]
connect_bd_net -net axi_ad9361_1_dac_data_0 [get_bd_pins axi_ad9361_1/dac_data_i0] [get_bd_pins util_dac_unpack_0/dac_data_04]
connect_bd_net -net axi_ad9361_1_dac_enable_1 [get_bd_pins axi_ad9361_1/dac_enable_q0] [get_bd_pins util_dac_unpack_0/dac_enable_05]
connect_bd_net -net axi_ad9361_1_dac_valid_1 [get_bd_pins axi_ad9361_1/dac_valid_q0] [get_bd_pins util_dac_unpack_0/dac_valid_05]
connect_bd_net -net axi_ad9361_1_dac_data_1 [get_bd_pins axi_ad9361_1/dac_data_q0] [get_bd_pins util_dac_unpack_0/dac_data_05]
connect_bd_net -net axi_ad9361_1_dac_enable_2 [get_bd_pins axi_ad9361_1/dac_enable_i1] [get_bd_pins util_dac_unpack_0/dac_enable_06]
connect_bd_net -net axi_ad9361_1_dac_valid_2 [get_bd_pins axi_ad9361_1/dac_valid_i1] [get_bd_pins util_dac_unpack_0/dac_valid_06]
connect_bd_net -net axi_ad9361_1_dac_data_2 [get_bd_pins axi_ad9361_1/dac_data_i1] [get_bd_pins util_dac_unpack_0/dac_data_06]
connect_bd_net -net axi_ad9361_1_dac_enable_3 [get_bd_pins axi_ad9361_1/dac_enable_q1] [get_bd_pins util_dac_unpack_0/dac_enable_07]
connect_bd_net -net axi_ad9361_1_dac_valid_3 [get_bd_pins axi_ad9361_1/dac_valid_q1] [get_bd_pins util_dac_unpack_0/dac_valid_07]
connect_bd_net -net axi_ad9361_1_dac_data_3 [get_bd_pins axi_ad9361_1/dac_data_q1] [get_bd_pins util_dac_unpack_0/dac_data_07]
connect_bd_net -net axi_ad9361_0_dac_drd [get_bd_pins util_dac_unpack_0/dma_rd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en]
connect_bd_net -net axi_ad9361_0_dac_ddata [get_bd_pins util_dac_unpack_0/dma_data] [get_bd_ports ad9361_0_dac_ddata]
connect_bd_net -net axi_ad9361_1_dac_ddata [get_bd_pins util_dac_unpack_1/dma_data] [get_bd_ports ad9361_1_dac_ddata]
connect_bd_net -net axi_ad9361_dac_ddata [get_bd_ports ad9361_dac_ddata] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9361_dac_ddata [get_bd_pins util_dac_unpack_0/dma_data] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9361_fifo_valid [get_bd_pins util_dac_unpack_0/fifo_valid] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid]
connect_bd_net -net axi_ad9361_0_adc_dovf [get_bd_pins axi_ad9361_0/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9361_0_dac_dunf [get_bd_pins axi_ad9361_0/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow]
@ -386,6 +371,7 @@ if {$xl_board eq "zc702"} {
set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE1_WIDTH {128}] $ila_adc_0
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_0
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins ila_adc_0/clk]
connect_bd_net -net axi_ad9361_0_dvalid [get_bd_pins ila_adc_0/probe0]
@ -402,6 +388,8 @@ if {$xl_board eq "zc702"} {
set_property -dict [list CONFIG.C_PROBE2_WIDTH {112}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_adc_0
set_property -dict [list CONFIG.C_PROBE4_WIDTH {128}] $ila_adc_0
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_0
connect_bd_net -net axi_ad9361_0_clk [get_bd_pins ila_adc_0/clk]
connect_bd_net -net axi_ad9361_0_dev_l_dbg_data [get_bd_pins axi_ad9361_0/dev_l_dbg_data] [get_bd_pins ila_adc_0/probe0]
@ -415,6 +403,7 @@ if {$xl_board eq "zc702"} {
set ila_adc_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_adc_1]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_adc_1
set_property -dict [list CONFIG.C_PROBE0_WIDTH {62}] $ila_adc_1
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc_1
connect_bd_net -net axi_ad9361_1_clk [get_bd_pins ila_adc_1/clk]
connect_bd_net -net axi_ad9361_1_dev_l_dbg_data [get_bd_pins axi_ad9361_1/dev_l_dbg_data] [get_bd_pins ila_adc_1/probe0]

10
projects/fmcomms5/zc706/system_top.v
View File

@ -248,10 +248,6 @@ module system_top (
wire gpio_open_45_45;
wire gpio_open_44_44;
wire gpio_open_15_15;
wire [ 63:0] ad9361_0_adc_ddata;
wire [ 63:0] ad9361_0_dac_ddata;
wire [ 63:0] ad9361_1_adc_ddata;
wire [ 63:0] ad9361_1_dac_ddata;
// multi-chip synchronization
@ -334,12 +330,6 @@ module system_top (
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.ad9361_0_adc_ddata (ad9361_0_adc_ddata),
.ad9361_0_dac_ddata (ad9361_0_dac_ddata),
.ad9361_1_adc_ddata (ad9361_1_adc_ddata),
.ad9361_1_dac_ddata (ad9361_1_dac_ddata),
.ad9361_adc_ddata ({ad9361_0_adc_ddata, ad9361_1_adc_ddata}),
.ad9361_dac_ddata ({ad9361_0_dac_ddata, ad9361_1_dac_ddata}),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),