From 7008c641b59dae55fe7e1f8a9515b4745de99a0c Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 11 Nov 2016 10:35:09 +0200 Subject: [PATCH] axi_adrv9371/zc706: Constraints update From source *jesd_rstgen* is a false path for TX and RX_OS too. --- projects/adrv9371x/zc706/system_constr.xdc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/projects/adrv9371x/zc706/system_constr.xdc b/projects/adrv9371x/zc706/system_constr.xdc index 49481db99..fa75a515d 100644 --- a/projects/adrv9371x/zc706/system_constr.xdc +++ b/projects/adrv9371x/zc706/system_constr.xdc @@ -75,4 +75,6 @@ create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/syste create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK] set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]