[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx

main
Istvan Csomortani 2017-08-28 15:12:07 +01:00
parent 3a47567f9c
commit 700ed156ab
11 changed files with 332 additions and 101 deletions

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@ -6,10 +6,10 @@ source ../../scripts/adi_ip_alt.tcl
ad_ip_create avl_dacfifo {Avalon DDR DAC Fifo}
set_module_property ELABORATION_CALLBACK p_avl_dacfifo
ad_ip_files avl_dacfifo [list\
$ad_hdl_dir/library/common/util_dacfifo_bypass.v \
$ad_hdl_dir/library/common/util_delay.v \
$ad_hdl_dir/library/common/ad_b2g.v \
$ad_hdl_dir/library/common/ad_g2b.v \
util_dacfifo_bypass.v \
avl_dacfifo_byteenable_coder.v \
avl_dacfifo_byteenable_decoder.v \
avl_dacfifo_wr.v \
@ -83,6 +83,28 @@ proc p_avl_dacfifo {} {
set m_avl_addr_width [get_parameter_value "AVL_ADDRESS_WIDTH"]
set m_dac_data_width [get_parameter_value "DAC_DATA_WIDTH"]
set m_dac_mem_addr_width [get_parameter_value "DAC_MEM_ADDRESS_WIDTH"]
set m_dac_mem_addr_width_bypass 10
if {$m_dma_data_width > $m_dac_data_width} {
set m_dma_to_dac_ratio [expr $m_dma_data_width/$m_dac_data_width]
if {$m_dma_to_dac_ratio eq 2} {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 1]
} elseif {$m_dma_to_dac_ratio eq 4} {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 2]
} else {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 3]
}
} else {
set m_dma_to_dac_ratio [expr $m_dac_data_width/$m_dma_data_width]
if {$m_dma_to_dac_ratio eq 1} {
set m_dma_mem_addr_width_bypass $m_dac_mem_addr_width_bypass
} elseif {$m_dma_to_dac_ratio eq 2} {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 1]
} elseif {$m_dma_to_dac_ratio eq 4} {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 2]
} else {
set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 3]
}
}
# altera memory for WRITE side
@ -101,5 +123,14 @@ proc p_avl_dacfifo {} {
set_instance_parameter_value alt_mem_asym_rd B_ADDRESS_WIDTH $m_dac_mem_addr_width
set_instance_parameter_value alt_mem_asym_rd B_DATA_WIDTH $m_dac_data_width
# altera memory for bypass logic
add_hdl_instance alt_mem_asym_bypass alt_mem_asym
set_instance_parameter_value alt_mem_asym_bypass DEVICE_FAMILY $m_device_family
set_instance_parameter_value alt_mem_asym_bypass A_ADDRESS_WIDTH $m_dma_mem_addr_width_bypass
set_instance_parameter_value alt_mem_asym_bypass A_DATA_WIDTH $m_dma_data_width
set_instance_parameter_value alt_mem_asym_bypass B_ADDRESS_WIDTH $m_dac_mem_addr_width_bypass
set_instance_parameter_value alt_mem_asym_bypass B_DATA_WIDTH $m_dac_data_width
}

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@ -0,0 +1,283 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_dacfifo_bypass #(
parameter DAC_DATA_WIDTH = 64,
parameter DMA_DATA_WIDTH = 64) (
// dma fifo interface
input dma_clk,
input [(DMA_DATA_WIDTH-1):0] dma_data,
input dma_ready,
output reg dma_ready_out,
input dma_valid,
// request and syncronizaiton
input dma_xfer_req,
// dac fifo interface
input dac_clk,
input dac_rst,
input dac_valid,
output reg [(DAC_DATA_WIDTH-1):0] dac_data,
output reg dac_dunf
);
// suported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1
localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH :
DAC_DATA_WIDTH/DMA_DATA_WIDTH;
localparam DAC_ADDRESS_WIDTH = 10;
localparam DMA_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH :
(MEM_RATIO == 2) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 1) : (DAC_ADDRESS_WIDTH + 1)) :
(MEM_RATIO == 4) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 2) : (DAC_ADDRESS_WIDTH + 2)) :
((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 3) : (DAC_ADDRESS_WIDTH + 3));
localparam DMA_BUF_THRESHOLD_HI = {(DMA_ADDRESS_WIDTH){1'b1}} - 4;
localparam DAC_BUF_THRESHOLD_LO = 4;
reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0;
reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0;
reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0;
reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0;
reg dma_rst_m1 = 1'b0;
reg dma_rst = 1'b0;
reg [DMA_ADDRESS_WIDTH-1:0] dma_mem_addr_diff = 1'b0;
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 1'b0;
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 1'b0;
reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr = 1'b0;
reg [DAC_ADDRESS_WIDTH-1:0] dac_mem_addr_diff = 1'b0;
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 1'b0;
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 1'b0;
reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr = 1'b0;
reg dac_mem_ready = 1'b0;
reg dac_xfer_out = 1'b0;
reg dac_xfer_out_m1 = 1'b0;
// internal signals
wire dma_mem_last_read_s;
wire [(DMA_ADDRESS_WIDTH):0] dma_mem_addr_diff_s;
wire [(DAC_ADDRESS_WIDTH):0] dac_mem_addr_diff_s;
wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_raddr_s;
wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_s;
wire dma_mem_wea_s;
wire dac_mem_rea_s;
wire [(DAC_DATA_WIDTH-1):0] dac_mem_rdata_s;
wire [DMA_ADDRESS_WIDTH:0] dma_address_diff_s;
wire [DAC_ADDRESS_WIDTH:0] dac_address_diff_s;
// binary to grey conversion
function [7:0] b2g;
input [7:0] b;
reg [7:0] g;
begin
g[7] = b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// grey to binary conversion
function [7:0] g2b;
input [7:0] g;
reg [7:0] b;
begin
b[7] = g[7];
b[6] = b[7] ^ g[6];
b[5] = b[6] ^ g[5];
b[4] = b[5] ^ g[4];
b[3] = b[4] ^ g[3];
b[2] = b[3] ^ g[2];
b[1] = b[2] ^ g[1];
b[0] = b[1] ^ g[0];
g2b = b;
end
endfunction
// An asymmetric memory to transfer data from DMAC interface to DAC interface
alt_mem_asym_bypass i_mem_asym (
.mem_i_wrclock (dma_clk),
.mem_i_wren (dma_mem_wea_s),
.mem_i_wraddress (dma_mem_waddr),
.mem_i_datain (dma_data),
.mem_i_rdclock (dac_clk),
.mem_i_rdaddress (dac_mem_raddr),
.mem_o_dataout (dac_mem_rdata_s));
// dma reset is brought from dac domain
always @(posedge dma_clk) begin
dma_rst_m1 <= dac_rst;
dma_rst <= dma_rst_m1;
end
// Write address generation for the asymmetric memory
assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_mem_waddr <= 'h0;
dma_mem_waddr_g <= 'h0;
end else begin
if (dma_mem_wea_s == 1'b1) begin
dma_mem_waddr <= dma_mem_waddr + 1;
end
dma_mem_waddr_g <= b2g(dma_mem_waddr);
end
end
// The memory module request data until reaches the high threshold.
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_mem_addr_diff <= 'b0;
dma_mem_raddr_m1 <= 'b0;
dma_mem_raddr_m2 <= 'b0;
dma_mem_raddr <= 'b0;
dma_ready_out <= 1'b0;
end else begin
dma_mem_raddr_m1 <= dac_mem_raddr_g;
dma_mem_raddr_m2 <= dma_mem_raddr_m1;
dma_mem_raddr <= g2b(dma_mem_raddr_m2);
dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0];
if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin
dma_ready_out <= 1'b0;
end else begin
dma_ready_out <= 1'b1;
end
end
end
// relative address offset on dma domain
assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
((MEM_RATIO == 1) ? (dma_mem_raddr) :
(MEM_RATIO == 2) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):1]) :
(MEM_RATIO == 4) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):2]) : (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):3])) :
((MEM_RATIO == 1) ? (dma_mem_raddr) :
(MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) :
(MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0}));
// relative address offset on dac domain
assign dac_address_diff_s = {1'b1, dac_mem_raddr} - dac_mem_waddr_s;
assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ?
((MEM_RATIO == 1) ? (dac_mem_waddr) :
(MEM_RATIO == 2) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):1]) :
(MEM_RATIO == 4) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):2]) : (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):3])) :
((MEM_RATIO == 1) ? (dac_mem_waddr) :
(MEM_RATIO == 2) ? ({dac_mem_waddr, 1'b0}) :
(MEM_RATIO == 4) ? ({dac_mem_waddr, 2'b0}) : ({dac_mem_waddr, 3'b0}));
// Read address generation for the asymmetric memory
assign dac_mem_rea_s = dac_valid & dac_mem_ready;
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_mem_raddr <= 'h0;
dac_mem_raddr_g <= 'h0;
end else begin
if (dac_mem_rea_s == 1'b1) begin
dac_mem_raddr <= dac_mem_raddr + 1;
end
dac_mem_raddr_g <= b2g(dac_mem_raddr);
end
end
// The memory module is ready if it's not empty
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_mem_addr_diff <= 'b0;
dac_mem_waddr_m1 <= 'b0;
dac_mem_waddr_m2 <= 'b0;
dac_mem_waddr <= 'b0;
dac_mem_ready <= 1'b0;
end else begin
dac_mem_waddr_m1 <= dma_mem_waddr_g;
dac_mem_waddr_m2 <= dac_mem_waddr_m1;
dac_mem_waddr <= g2b(dac_mem_waddr_m2);
dac_mem_addr_diff <= dac_address_diff_s[DAC_ADDRESS_WIDTH-1:0];
if (dac_mem_addr_diff > 0) begin
dac_mem_ready <= 1'b1;
end else begin
dac_mem_ready <= 1'b0;
end
end
end
// define underflow
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_xfer_out_m1 <= 1'b0;
dac_xfer_out <= 1'b0;
dac_dunf <= 1'b0;
end else begin
dac_xfer_out_m1 <= dma_xfer_req;
dac_xfer_out <= dac_xfer_out_m1;
dac_dunf <= (dac_valid == 1'b1) ? (dac_xfer_out & ~dac_mem_ready) : dac_dunf;
end
end
// DAC data output logic
always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin
dac_data <= 0;
end else begin
dac_data <= dac_mem_rdata_s;
end
end
endmodule

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@ -8,9 +8,6 @@
M_DEPS += ../../common/ad_axis_inf_rx.v
M_DEPS += ../../common/ad_b2g.v
M_DEPS += ../../common/ad_g2b.v
M_DEPS += ../../common/ad_mem_asym.v
M_DEPS += ../../common/ad_mem.v
M_DEPS += ../../common/util_dacfifo_bypass.v
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_ip.tcl
M_DEPS += axi_dacfifo.v
@ -19,6 +16,7 @@ M_DEPS += axi_dacfifo_ip.tcl
M_DEPS += axi_dacfifo_rd.v
M_DEPS += axi_dacfifo_address_buffer.v
M_DEPS += axi_dacfifo_wr.v
M_DEPS += util_dacfifo_bypass.v
M_VIVADO := vivado -mode batch -source

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@ -11,8 +11,8 @@ adi_ip_files axi_dacfifo [list \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/ad_mem.v" \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"$ad_hdl_dir/library/common/util_dacfifo_bypass.v" \
"axi_dacfifo_constr.xdc" \
"util_dacfifo_bypass.v" \
"axi_dacfifo_wr.v" \
"axi_dacfifo_rd.v" \
"axi_dacfifo_address_buffer.v" \

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@ -9,19 +9,25 @@
all:
-make -C a10gx all
-make -C a10soc all
-make -C kcu105 all
-make -C zc706 all
-make -C zcu102 all
clean:
make -C a10gx clean
make -C a10soc clean
make -C kcu105 clean
make -C zc706 clean
make -C zcu102 clean
clean-all:
make -C a10gx clean-all
make -C a10soc clean-all
make -C kcu105 clean-all
make -C zc706 clean-all
make -C zcu102 clean-all
####################################################################################
####################################################################################

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@ -79,32 +79,6 @@ M_DEPS += ../../../library/common/up_dac_channel.v
M_DEPS += ../../../library/common/up_dac_common.v
M_DEPS += ../../../library/common/up_xfer_cntrl.v
M_DEPS += ../../../library/common/up_xfer_status.v
M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_common.v
M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
M_DEPS += ../../../library/jesd204/jesd204_common/eof.v
M_DEPS += ../../../library/jesd204/jesd204_common/lmfc.v
M_DEPS += ../../../library/jesd204/jesd204_common/pipeline_stage.v
M_DEPS += ../../../library/jesd204/jesd204_common/scrambler.v
M_DEPS += ../../../library/jesd204/jesd204_rx/align_mux.v
M_DEPS += ../../../library/jesd204/jesd204_rx/elastic_buffer.v
M_DEPS += ../../../library/jesd204/jesd204_rx/ilas_monitor.v
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_rx/lane_latency_monitor.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx_cgs.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx_ctrl.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx_lane.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/8b10b_decoder.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
@ -112,11 +86,6 @@ M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/pattern_align.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/8b10b_encoder.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_tx/tx.v
M_DEPS += ../../../library/jesd204/jesd204_tx/tx_ctrl.v
M_DEPS += ../../../library/jesd204/jesd204_tx/tx_lane.v
M_DEPS += ../../../library/scripts/adi_env.tcl
M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
@ -125,8 +94,6 @@ M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_data.v
M_DEPS += ../../../library/util_cdc/sync_event.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v

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@ -31,6 +31,7 @@ M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_constr.sdc
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_hw.tcl
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_rd.v
M_DEPS += ../../../library/altera/avl_dacfifo/avl_dacfifo_wr.v
M_DEPS += ../../../library/altera/avl_dacfifo/util_dacfifo_bypass.v
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
@ -88,34 +89,7 @@ M_DEPS += ../../../library/common/up_dac_channel.v
M_DEPS += ../../../library/common/up_dac_common.v
M_DEPS += ../../../library/common/up_xfer_cntrl.v
M_DEPS += ../../../library/common/up_xfer_status.v
M_DEPS += ../../../library/common/util_dacfifo_bypass.v
M_DEPS += ../../../library/common/util_delay.v
M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_common.v
M_DEPS += ../../../library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
M_DEPS += ../../../library/jesd204/jesd204_common/eof.v
M_DEPS += ../../../library/jesd204/jesd204_common/lmfc.v
M_DEPS += ../../../library/jesd204/jesd204_common/pipeline_stage.v
M_DEPS += ../../../library/jesd204/jesd204_common/scrambler.v
M_DEPS += ../../../library/jesd204/jesd204_rx/align_mux.v
M_DEPS += ../../../library/jesd204/jesd204_rx/elastic_buffer.v
M_DEPS += ../../../library/jesd204/jesd204_rx/ilas_monitor.v
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_rx/lane_latency_monitor.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx_cgs.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx_ctrl.v
M_DEPS += ../../../library/jesd204/jesd204_rx/rx_lane.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/8b10b_decoder.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
@ -123,11 +97,6 @@ M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_rx/pattern_align.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/8b10b_encoder.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
M_DEPS += ../../../library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
M_DEPS += ../../../library/jesd204/jesd204_tx/tx.v
M_DEPS += ../../../library/jesd204/jesd204_tx/tx_ctrl.v
M_DEPS += ../../../library/jesd204/jesd204_tx/tx_lane.v
M_DEPS += ../../../library/scripts/adi_env.tcl
M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
M_DEPS += ../../../library/util_axis_fifo/address_gray.v
@ -136,8 +105,6 @@ M_DEPS += ../../../library/util_axis_fifo/address_sync.v
M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/util_cdc/sync_data.v
M_DEPS += ../../../library/util_cdc/sync_event.v
M_DEPS += ../../../library/util_cdc/sync_gray.v
M_DEPS += ../../../library/util_cpack/util_cpack.v
M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v

View File

@ -13,6 +13,9 @@ M_DEPS += ../common/adrv9371x_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
M_DEPS += ../../common/kcu105/kcu105_system_lutram_constr.xdc
M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
@ -20,17 +23,14 @@ M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/axi_ad9371/axi_ad9371.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx.xpr
M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_VIVADO := vivado -mode batch -source
@ -63,17 +63,14 @@ clean-all:clean
make -C ../../../library/axi_ad9371 clean
make -C ../../../library/xilinx/axi_adxcvr clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/xilinx/axi_dacfifo clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/jesd204/axi_jesd204_rx clean
make -C ../../../library/jesd204/axi_jesd204_tx clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/jesd204/jesd204_rx clean
make -C ../../../library/jesd204/jesd204_tx clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_dacfifo clean
make -C ../../../library/util_upack clean
@ -86,17 +83,14 @@ lib:
make -C ../../../library/axi_ad9371
make -C ../../../library/xilinx/axi_adxcvr
make -C ../../../library/axi_clkgen
make -C ../../../library/xilinx/axi_dacfifo
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/jesd204/axi_jesd204_rx
make -C ../../../library/jesd204/axi_jesd204_tx
make -C ../../../library/axi_spdif_tx
make -C ../../../library/jesd204/jesd204_rx
make -C ../../../library/jesd204/jesd204_tx
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_bsplit
make -C ../../../library/util_cpack
make -C ../../../library/util_dacfifo
make -C ../../../library/util_upack
####################################################################################

View File

@ -31,7 +31,6 @@ M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx.xpr
M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
@ -74,7 +73,6 @@ clean-all:clean
make -C ../../../library/jesd204/jesd204_rx clean
make -C ../../../library/jesd204/jesd204_tx clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_upack clean
@ -97,7 +95,6 @@ lib:
make -C ../../../library/jesd204/jesd204_rx
make -C ../../../library/jesd204/jesd204_tx
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_bsplit
make -C ../../../library/util_cpack
make -C ../../../library/util_upack

View File

@ -15,22 +15,18 @@ M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
M_DEPS += ../../../library/axi_ad9371/axi_ad9371.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/xilinx/axi_dacfifo/axi_dacfifo.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr
M_DEPS += ../../../library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/jesd204/jesd204_rx/jesd204_rx.xpr
M_DEPS += ../../../library/jesd204/jesd204_tx/jesd204_tx.xpr
M_DEPS += ../../../library/util_adcfifo/util_adcfifo.xpr
M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
M_DEPS += ../../../library/util_bsplit/util_bsplit.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_dacfifo/util_dacfifo.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
@ -65,17 +61,14 @@ clean-all:clean
make -C ../../../library/axi_ad9371 clean
make -C ../../../library/xilinx/axi_adxcvr clean
make -C ../../../library/axi_clkgen clean
make -C ../../../library/xilinx/axi_dacfifo clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/jesd204/axi_jesd204_rx clean
make -C ../../../library/jesd204/axi_jesd204_tx clean
make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/jesd204/jesd204_rx clean
make -C ../../../library/jesd204/jesd204_tx clean
make -C ../../../library/xilinx/util_adxcvr clean
make -C ../../../library/util_bsplit clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_dacfifo clean
make -C ../../../library/util_upack clean
@ -88,17 +81,12 @@ lib:
make -C ../../../library/axi_ad9371
make -C ../../../library/xilinx/axi_adxcvr
make -C ../../../library/axi_clkgen
make -C ../../../library/xilinx/axi_dacfifo
make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx
make -C ../../../library/jesd204/axi_jesd204_rx
make -C ../../../library/jesd204/axi_jesd204_tx
make -C ../../../library/axi_spdif_tx
make -C ../../../library/jesd204/jesd204_rx
make -C ../../../library/jesd204/jesd204_tx
make -C ../../../library/util_adcfifo
make -C ../../../library/xilinx/util_adxcvr
make -C ../../../library/util_bsplit
make -C ../../../library/util_cpack
make -C ../../../library/util_dacfifo
make -C ../../../library/util_upack