ad_ip_jesd204_tpl_dac: Move external dac sync bit

library/common/up_dac_common.v

@@ -64,6 +64,7 @@ module up_dac_common #(
   output              dac_symb_op,
   output              dac_symb_8_16b,
   output              dac_sync,
+  output              dac_ext_sync_arm,
   output              dac_frame,
   output              dac_clksel,
   output              dac_par_type,
@@ -126,6 +127,7 @@ module up_dac_common #(
   reg             up_mmcm_resetn = 'd0;
   reg             up_resetn = 'd0;
   reg             up_dac_sync = 'd0;
+  reg             up_dac_ext_sync_arm = 'd0;
   reg      [4:0]  up_dac_num_lanes = 'd0;
   reg             up_dac_sdr_ddr_n = 'd0;
   reg             up_dac_symb_op = 'd0;
@@ -190,6 +192,7 @@ module up_dac_common #(
       up_mmcm_resetn <= 'd0;
       up_resetn <= 'd0;
       up_dac_sync <= 'd0;
+      up_dac_ext_sync_arm <= 'd0;
       up_dac_num_lanes <= 'd0;
       up_dac_sdr_ddr_n <= 'd0;
       up_dac_symb_op <= 'd0;
@@ -225,6 +228,13 @@ module up_dac_common #(
       end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin
         up_dac_sync <= up_wdata[0];
       end
+      if (up_dac_ext_sync_arm == 1'b1) begin
+        if (up_xfer_done_s == 1'b1) begin
+          up_dac_ext_sync_arm <= 1'b0;
+        end
+      end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin
+        up_dac_ext_sync_arm <= up_wdata[1];
+      end
       if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin
         up_dac_sdr_ddr_n <= up_wdata[16];
         up_dac_symb_op <= up_wdata[15];
@@ -403,7 +413,7 @@ module up_dac_common #(
           7'h03: up_rdata_int <= CONFIG;
           7'h07: up_rdata_int <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8]
           7'h10: up_rdata_int <= {29'd0, up_dac_clk_enb, up_mmcm_resetn, up_resetn};
-          7'h11: up_rdata_int <= {31'd0, up_dac_sync};
+          7'h11: up_rdata_int <= {30'd0, up_dac_ext_sync_arm, up_dac_sync};
           7'h12: up_rdata_int <= {15'd0, up_dac_sdr_ddr_n,
                                   up_dac_symb_op, up_dac_symb_8_16b,
                                   1'd0, up_dac_num_lanes,
@@ -442,13 +452,14 @@ module up_dac_common #(
 
   // dac control & status
 
-  up_xfer_cntrl #(.DATA_WIDTH(32)) i_xfer_cntrl (
+  up_xfer_cntrl #(.DATA_WIDTH(33)) i_xfer_cntrl (
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_data_cntrl ({ up_dac_sdr_ddr_n,
                       up_dac_symb_op,
                       up_dac_symb_8_16b,
                       up_dac_num_lanes,
+                      up_dac_ext_sync_arm,
                       up_dac_sync,
                       up_dac_clksel,
                       up_dac_frame,
@@ -465,6 +476,7 @@ module up_dac_common #(
                       dac_symb_op,
                       dac_symb_8_16b,
                       dac_num_lanes,
+                      dac_ext_sync_arm,
                       dac_sync_s,
                       dac_clksel,
                       dac_frame_s,

library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v

@@ -103,6 +103,7 @@ module ad_ip_jesd204_tpl_dac #(
   // internal signals
 
   wire dac_sync;
+  wire dac_ext_sync_arm;
   wire dac_sync_in_status;
   wire dac_dds_format;
 
@@ -167,6 +168,7 @@ module ad_ip_jesd204_tpl_dac #(
     .dac_dunf (dac_dunf),
 
     .dac_sync (dac_sync),
+    .dac_ext_sync_arm (dac_ext_sync_arm),
     .dac_sync_in_status (dac_sync_in_status),
     .dac_dds_format (dac_dds_format),
 
@@ -227,6 +229,7 @@ module ad_ip_jesd204_tpl_dac #(
     .dac_ddata (dac_ddata_cr),
 
     .dac_sync (dac_sync),
+    .dac_ext_sync_arm (dac_ext_sync_arm),
     .dac_sync_in_status (dac_sync_in_status),
     .dac_sync_in (dac_sync_in),
     .dac_dds_format (dac_dds_format),

library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v

@@ -54,6 +54,7 @@ module ad_ip_jesd204_tpl_dac_core #(
   // Configuration interface
 
   input dac_sync,
+  input dac_ext_sync_arm,
 
   input dac_sync_in,
 
@@ -94,25 +95,31 @@ module ad_ip_jesd204_tpl_dac_core #(
 
   reg dac_sync_in_d1 ='d0;
   reg dac_sync_in_d2 ='d0;
-  reg dac_sync_in_arm ='d0;
+  reg dac_sync_in_armed ='d0;
-  reg dac_sync_d1 = 'd0;
+  reg dac_ext_sync_arm_d1 = 'd0;
 
   assign link_valid = 1'b1;
-  assign dac_sync_in_status = dac_sync_in_arm;
+  assign dac_sync_in_status = dac_sync_in_armed;
 
+  // External sync
   always @(posedge clk) begin
-    dac_sync_d1 <= dac_sync;
+    dac_ext_sync_arm_d1 <= dac_ext_sync_arm;
+
     dac_sync_in_d1 <= dac_sync_in;
     dac_sync_in_d2 <= dac_sync_in_d1;
-    if ((~dac_sync_d1&dac_sync) == 1'b1) begin
+
-      dac_sync_in_arm <= ~dac_sync_in_arm;
+    if (EXT_SYNC == 1'b0) begin
-    end else if ((~dac_sync_in_d2&dac_sync_in_d1) == 1'b1) begin
+      dac_sync_in_armed <= 1'b0;
-      dac_sync_in_arm <= 1'b0;
+    end else if (~dac_ext_sync_arm_d1 & dac_ext_sync_arm) begin
-    end else if (EXT_SYNC == 1'b0) begin
+      dac_sync_in_armed <= ~dac_sync_in_armed;
-      dac_sync_in_arm <= 1'b0;
+    end else if (~dac_sync_in_d2 & dac_sync_in_d1) begin
+      dac_sync_in_armed <= 1'b0;
     end
   end
 
+  // Sync either from external or software source
+  assign dac_sync_int = dac_sync_in_armed | dac_sync;
+
   // device interface
 
   ad_ip_jesd204_tpl_dac_framer #(
@@ -135,7 +142,7 @@ module ad_ip_jesd204_tpl_dac_core #(
     .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION)
   ) i_pn_gen (
     .clk (clk),
-    .reset (dac_sync_in_arm),
+    .reset (dac_sync_int),
 
     .pn7_data (pn7_data),
     .pn15_data (pn15_data)
@@ -143,7 +150,7 @@ module ad_ip_jesd204_tpl_dac_core #(
 
   // dac valid
 
-  assign dac_valid = {NUM_CHANNELS{~dac_sync_in_arm}};
+  assign dac_valid = {NUM_CHANNELS{~dac_sync_int}};
 
   generate
   genvar i;
@@ -192,7 +199,7 @@ module ad_ip_jesd204_tpl_dac_core #(
       .pn7_data (pn7_data),
       .pn15_data (pn15_data),
 
-      .dac_data_sync (dac_sync_in_arm),
+      .dac_data_sync (dac_sync_int),
       .dac_dds_format (dac_dds_format),
 
       .dac_data_sel (dac_data_sel[4*i+:4]),

library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v

@@ -69,6 +69,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
   input dac_dunf,
 
   output dac_sync,
+  output dac_ext_sync_arm,
 
   input dac_sync_in_status,
 
@@ -210,6 +211,7 @@ module ad_ip_jesd204_tpl_dac_regmap #(
     .dac_clk (link_clk),
     .dac_rst (dac_rst),
     .dac_sync (dac_sync),
+    .dac_ext_sync_arm (dac_ext_sync_arm),
     .dac_sync_in_status (dac_sync_in_status),
     .dac_frame (),
     .dac_clksel (),