kcu105: ip automatic version update
Adrian Costina
parent
942d69a30c
commit
71394ee465
|
|
@ -51,85 +51,86 @@ set_property -dict [list CONFIG.FREQ_HZ {625000000}] [get_bd_intf_ports phy_clk]
|
|||
|
||||
# instance: microblaze - processor
|
||||
|
||||
set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.6 sys_mb]
|
||||
set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb
|
||||
set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb
|
||||
ad_ip_instance microblaze sys_mb
|
||||
ad_ip_parameter sys_mb CONFIG.G_TEMPLATE_LIST 4
|
||||
ad_ip_parameter sys_mb CONFIG.C_DCACHE_FORCE_TAG_LUTRAM 1
|
||||
|
||||
# instance: microblaze - local memory & bus
|
||||
|
||||
set sys_dlmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_dlmb]
|
||||
set sys_ilmb [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 sys_ilmb]
|
||||
ad_ip_instance lmb_v10 sys_dlmb
|
||||
ad_ip_instance lmb_v10 sys_ilmb
|
||||
|
||||
set sys_dlmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_dlmb_cntlr]
|
||||
set_property -dict [list CONFIG.C_ECC {0}] $sys_dlmb_cntlr
|
||||
ad_ip_instance lmb_bram_if_cntlr sys_dlmb_cntlr
|
||||
ad_ip_parameter sys_dlmb_cntlr CONFIG.C_ECC 0
|
||||
|
||||
set sys_ilmb_cntlr [create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 sys_ilmb_cntlr]
|
||||
set_property -dict [list CONFIG.C_ECC {0}] $sys_ilmb_cntlr
|
||||
ad_ip_instance lmb_bram_if_cntlr sys_ilmb_cntlr
|
||||
ad_ip_parameter sys_ilmb_cntlr CONFIG.C_ECC 0
|
||||
|
||||
set sys_lmb_bram [create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 sys_lmb_bram]
|
||||
set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram_block {BRAM_Controller}] $sys_lmb_bram
|
||||
ad_ip_instance blk_mem_gen sys_lmb_bram
|
||||
ad_ip_parameter sys_lmb_bram CONFIG.Memory_Type True_Dual_Port_RAM
|
||||
ad_ip_parameter sys_lmb_bram CONFIG.use_bram_block BRAM_Controller
|
||||
|
||||
# instance: microblaze- mdm
|
||||
|
||||
set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 sys_mb_debug]
|
||||
set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug
|
||||
ad_ip_instance mdm sys_mb_debug
|
||||
ad_ip_parameter sys_mb_debug CONFIG.C_USE_UART 1
|
||||
|
||||
# instance: system reset/clocks
|
||||
|
||||
set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
|
||||
ad_ip_instance proc_sys_reset sys_rstgen
|
||||
|
||||
# instance: ddr4
|
||||
|
||||
set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.0 axi_ddr_cntrl]
|
||||
set_property -dict [list CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_300}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] $axi_ddr_cntrl
|
||||
ad_ip_instance ip:ddr4 axi_ddr_cntrl
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_CLOCK_BOARD_INTERFACE default_sysclk_300
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.C0_DDR4_BOARD_INTERFACE ddr4_sdram
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.RESET_BOARD_INTERFACE reset
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ 200
|
||||
|
||||
set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_ddr_cntrl_rstgen]
|
||||
ad_ip_instance proc_sys_reset axi_ddr_cntrl_rstgen
|
||||
|
||||
# instance: default peripherals
|
||||
|
||||
set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:7.0 axi_ethernet]
|
||||
set_property -dict [list CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet
|
||||
set_property -dict [list CONFIG.RXMEM {8k}] $axi_ethernet
|
||||
ad_ip_instance axi_ethernet axi_ethernet
|
||||
ad_ip_parameter axi_ethernet CONFIG.ETHERNET_BOARD_INTERFACE sgmii_lvds
|
||||
ad_ip_parameter axi_ethernet CONFIG.MDIO_BOARD_INTERFACE mdio_mdc
|
||||
ad_ip_parameter axi_ethernet CONFIG.DIFFCLK_BOARD_INTERFACE sgmii_phyclk
|
||||
ad_ip_parameter axi_ethernet CONFIG.PHYRST_BOARD_INTERFACE phy_reset_out
|
||||
ad_ip_parameter axi_ethernet CONFIG.TXCSUM Full
|
||||
ad_ip_parameter axi_ethernet CONFIG.RXCSUM Full
|
||||
ad_ip_parameter axi_ethernet CONFIG.TXMEM 8k
|
||||
ad_ip_parameter axi_ethernet CONFIG.RXMEM 8k
|
||||
|
||||
set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
|
||||
set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma
|
||||
set_property -dict [list CONFIG.c_sg_use_stsapp_length {1}] $axi_ethernet_dma
|
||||
set_property -dict [list CONFIG.c_include_s2mm_dre {1}] $axi_ethernet_dma
|
||||
ad_ip_instance axi_dma axi_ethernet_dma
|
||||
ad_ip_parameter axi_ethernet_dma CONFIG.c_include_mm2s_dre 1
|
||||
ad_ip_parameter axi_ethernet_dma CONFIG.c_sg_use_stsapp_length 1
|
||||
ad_ip_parameter axi_ethernet_dma CONFIG.c_include_s2mm_dre 1
|
||||
|
||||
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
|
||||
ad_ip_instance axi_iic axi_iic_main
|
||||
|
||||
set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
|
||||
set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
|
||||
ad_ip_instance axi_uartlite axi_uart
|
||||
ad_ip_parameter axi_uart CONFIG.C_BAUDRATE 115200
|
||||
|
||||
set axi_timer [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer]
|
||||
ad_ip_instance axi_timer axi_timer
|
||||
|
||||
set axi_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_spi]
|
||||
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_spi
|
||||
set_property -dict [list CONFIG.C_NUM_SS_BITS {8}] $axi_spi
|
||||
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_spi
|
||||
ad_ip_instance axi_quad_spi axi_spi
|
||||
ad_ip_parameter axi_spi CONFIG.C_USE_STARTUP 0
|
||||
ad_ip_parameter axi_spi CONFIG.C_NUM_SS_BITS 8
|
||||
ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 8
|
||||
|
||||
set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio]
|
||||
set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio
|
||||
set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio
|
||||
set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $axi_gpio
|
||||
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio
|
||||
ad_ip_instance axi_gpio axi_gpio
|
||||
ad_ip_parameter axi_gpio CONFIG.C_IS_DUAL 1
|
||||
ad_ip_parameter axi_gpio CONFIG.C_GPIO_WIDTH 32
|
||||
ad_ip_parameter axi_gpio CONFIG.C_GPIO2_WIDTH 32
|
||||
ad_ip_parameter axi_gpio CONFIG.C_INTERRUPT_PRESENT 1
|
||||
|
||||
# instance: interrupt
|
||||
|
||||
set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc]
|
||||
set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
|
||||
ad_ip_instance axi_intc axi_intc
|
||||
ad_ip_parameter axi_intc CONFIG.C_HAS_FAST 0
|
||||
|
||||
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
|
||||
set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
|
||||
ad_ip_instance xlconcat sys_concat_intc
|
||||
ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16
|
||||
|
||||
# ddr4
|
||||
|
||||
|
|
|
|||
|
|
@ -1,17 +1,15 @@
|
|||
|
||||
# ddr controller RevD
|
||||
|
||||
set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.C0.DDR4_TimePeriod {833}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.C0.DDR4_InputClockPeriod {3332}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.C0.DDR4_MemoryPart {EDY4016AABG-DR-F}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.C0.DDR4_DataWidth {64}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.C0.DDR4_CasWriteLatency {12}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.Debug_Signal {Enable}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.C0.DDR4_AxiDataWidth {512}] $axi_ddr_cntrl
|
||||
|
||||
set_property -dict [list CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100}] $axi_ddr_cntrl
|
||||
set_property -dict [list CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {200}] $axi_ddr_cntrl
|
||||
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.C0.ControllerType DDR4_SDRAM
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_TimePeriod 833
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_InputClockPeriod 3332
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_MemoryPart EDY4016AABG-DR-F
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_DataWidth 64
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_Mem_Add_Map ROW_COLUMN_BANK
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_CasWriteLatency 12
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.Debug_Signal Enable
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.C0.DDR4_AxiDataWidth 512
|
||||
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ 100
|
||||
ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ 200
|
||||
|
|
|
|||
Loading…
Reference in New Issue