Add a helper module to combine a AXI read-only and a AXI write-only interface into a read-write interface
The read and write interfaces of a AXI bus are independent other than that they use the same clock. Yet when connecting a single read-only and a single write-only interface to a Xilinx AXI interconnect it instantiates arbitration logic between the two interfaces. This is dead logic and unnecessarily utilizes the FPGAs resources. Introduce a new helper module that takes a read-only and a write-only AXI interface and combines them into a single read-write interface. The only restriction here is that all three interfaces need to use the same clock. This module is useful for systems which feature a read DMA and a write DMA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
parent
3e0b337eae
commit
71469490c6
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@ -46,6 +46,7 @@ clean:
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make -C axi_mc_controller clean
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make -C axi_mc_current_monitor clean
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make -C axi_mc_speed clean
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make -C axi_rd_wr_combiner clean
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make -C axi_spdif_rx clean
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make -C axi_spdif_tx clean
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make -C axi_usb_fx3 clean
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@ -127,6 +128,7 @@ lib:
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-make -C axi_mc_controller
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-make -C axi_mc_current_monitor
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-make -C axi_mc_speed
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-make -C axi_rd_wr_combiner
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-make -C axi_spdif_rx
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-make -C axi_spdif_tx
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-make -C axi_usb_fx3
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@ -0,0 +1,42 @@
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += axi_rd_wr_combiner.v
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += component.xml
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.ip_user_files
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M_FLIST += *.srcs
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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.PHONY: all dep clean clean-all
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all: dep axi_rd_wr_combiner.xpr
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clean:clean-all
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clean-all:
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rm -rf $(M_FLIST)
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axi_rd_wr_combiner.xpr: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) axi_rd_wr_combiner_ip.tcl >> axi_rd_wr_combiner_ip.log 2>&1
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####################################################################################
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####################################################################################
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@ -0,0 +1,156 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2017(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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/*
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* Helper module to combine a read-only and a write-only AXI interface into a
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* single read-write AXI interface. Only supports AXI3 at the moment.
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*/
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module axi_rd_wr_combiner (
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input clk,
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// Master write address
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output [31:0] m_axi_awaddr,
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output [ 3:0] m_axi_awlen,
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output [ 2:0] m_axi_awsize,
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output [ 1:0] m_axi_awburst,
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output [ 2:0] m_axi_awprot,
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output [ 3:0] m_axi_awcache,
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output m_axi_awvalid,
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input m_axi_awready,
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// Master write data
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output [63:0] m_axi_wdata,
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output [ 7:0] m_axi_wstrb,
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input m_axi_wready,
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output m_axi_wvalid,
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output m_axi_wlast,
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// Master write response
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input m_axi_bvalid,
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input [ 1:0] m_axi_bresp,
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output m_axi_bready,
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// Master read address
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output m_axi_arvalid,
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output [31:0] m_axi_araddr,
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output [ 3:0] m_axi_arlen,
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output [ 2:0] m_axi_arsize,
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output [ 1:0] m_axi_arburst,
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output [ 3:0] m_axi_arcache,
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output [ 2:0] m_axi_arprot,
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input m_axi_arready,
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// Master read response + data
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input m_axi_rvalid,
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input [ 1:0] m_axi_rresp,
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input [63:0] m_axi_rdata,
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output m_axi_rready,
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// Slave write address
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input [31:0] s_wr_axi_awaddr,
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input [ 3:0] s_wr_axi_awlen,
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input [ 2:0] s_wr_axi_awsize,
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input [ 1:0] s_wr_axi_awburst,
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input [ 2:0] s_wr_axi_awprot,
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input [ 3:0] s_wr_axi_awcache,
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input s_wr_axi_awvalid,
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output s_wr_axi_awready,
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// Salve write data
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input [63:0] s_wr_axi_wdata,
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input [ 7:0] s_wr_axi_wstrb,
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output s_wr_axi_wready,
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input s_wr_axi_wvalid,
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input s_wr_axi_wlast,
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// Slave write response
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output s_wr_axi_bvalid,
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output [ 1:0] s_wr_axi_bresp,
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input s_wr_axi_bready,
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// Slave read address
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input s_rd_axi_arvalid,
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input [31:0] s_rd_axi_araddr,
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input [ 3:0] s_rd_axi_arlen,
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input [ 2:0] s_rd_axi_arsize,
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input [ 1:0] s_rd_axi_arburst,
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input [ 3:0] s_rd_axi_arcache,
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input [ 2:0] s_rd_axi_arprot,
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output s_rd_axi_arready,
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// Slave read response + data
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output s_rd_axi_rvalid,
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output [ 1:0] s_rd_axi_rresp,
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output [63:0] s_rd_axi_rdata,
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input s_rd_axi_rready
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);
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assign m_axi_awaddr = s_wr_axi_awaddr;
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assign m_axi_awlen = s_wr_axi_awlen;
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assign m_axi_awsize = s_wr_axi_awsize;
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assign m_axi_awburst = s_wr_axi_awburst;
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assign m_axi_awprot = s_wr_axi_awprot;
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assign m_axi_awcache = s_wr_axi_awcache;
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assign m_axi_awvalid = s_wr_axi_awvalid;
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assign s_wr_axi_awready = m_axi_awready;
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assign m_axi_wdata = s_wr_axi_wdata;
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assign m_axi_wstrb = s_wr_axi_wstrb;
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assign s_wr_axi_wready = m_axi_wready;
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assign m_axi_wvalid = s_wr_axi_wvalid;
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assign m_axi_wlast = s_wr_axi_wlast;
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assign s_wr_axi_bvalid = m_axi_bvalid;
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assign s_wr_axi_bresp = m_axi_bresp;
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assign m_axi_bready = s_wr_axi_bready;
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assign m_axi_arvalid = s_rd_axi_arvalid;
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assign m_axi_araddr = s_rd_axi_araddr;
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assign m_axi_arlen = s_rd_axi_arlen;
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assign m_axi_arsize = s_rd_axi_arsize;
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assign m_axi_arburst = s_rd_axi_arburst;
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assign m_axi_arcache = s_rd_axi_arcache;
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assign m_axi_arprot = s_rd_axi_arprot;
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assign s_rd_axi_arready = m_axi_arready;
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assign s_rd_axi_rvalid = m_axi_rvalid;
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assign s_rd_axi_rresp = m_axi_rresp;
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assign s_rd_axi_rdata = m_axi_rdata;
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assign m_axi_rready = s_rd_axi_rready;
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endmodule
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@ -0,0 +1,18 @@
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# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_rd_wr_combiner
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adi_ip_files axi_rd_wr_combiner [list \
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"axi_rd_wr_combiner.v" \
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]
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adi_ip_properties_lite axi_rd_wr_combiner
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adi_ip_infer_mm_interfaces axi_rd_wr_combiner
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# Dummy clock to helper with clock rate and clock domain propagation to the
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# interface
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adi_add_bus_clock "clk" "m_axi:s_wr_axi:s_rd_axi"
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ipx::save_core [ipx::current_core]
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Loading…
Reference in New Issue