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jesd204: Expose core synthesis parameters through registers 

Make synthesis parameters accessible for the drivers.
Rework implementation to reflect the parameters of the actual core and
not of the AXI interfacing core.
main
Laszlo Nagy 2020-12-03 13:59:33 +00:00 committed by Laszlo Nagy
parent 454b900f90
commit 71475e7dd8
10 changed files with 88 additions and 16 deletions
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13
library/jesd204/axi_jesd204_common/jesd204_up_common.v
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@ -54,7 +54,6 @@ module jesd204_up_common # (
parameter NUM_IRQS = 1,
parameter EXTRA_CFG_WIDTH = 1,
parameter DEV_EXTRA_CFG_WIDTH = 1,
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
parameter ENABLE_LINK_STATS = 0
) (
input up_clk,
@ -98,7 +97,11 @@ module jesd204_up_common # (
output reg [9:0] device_cfg_octets_per_multiframe = 'h00,
output reg [7:0] device_cfg_octets_per_frame = 'h00,
output reg [7:0] device_cfg_beats_per_multiframe = 'h00
output reg [7:0] device_cfg_beats_per_multiframe = 'h00,
input [31:0] status_synth_params0,
input [31:0] status_synth_params1,
input [31:0] status_synth_params2
);
reg [31:0] up_scratch = 32'h00000000;
@ -296,9 +299,9 @@ always @(*) begin
12'h003: up_rdata = PCORE_MAGIC;
/* Core configuration */
12'h004: up_rdata = NUM_LANES;
12'h005: up_rdata = DATA_PATH_WIDTH_LOG2;
12'h006: up_rdata = {22'b0,LINK_MODE[1:0], NUM_LINKS[7:0]};
12'h004: up_rdata = status_synth_params0;
12'h005: up_rdata = status_synth_params1;
12'h006: up_rdata = status_synth_params2;
/* 0x07-0x0f reserved for future use */
/* 0x10-0x1f reserved for core specific HDL configuration information */

15
library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
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@ -120,7 +120,11 @@ module axi_jesd204_rx #(
input [3*NUM_LANES-1:0] core_status_lane_emb_state,
input [NUM_LANES-1:0] core_status_lane_ifs_ready,
input [14*NUM_LANES-1:0] core_status_lane_latency,
input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt
input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt,
input [31:0] status_synth_params0,
input [31:0] status_synth_params1,
input [31:0] status_synth_params2
);
localparam PCORE_VERSION = 32'h00010661; // 1.06.a
@ -211,11 +215,9 @@ jesd204_up_common #(
.ID(ID),
.NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS),
.DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2),
.NUM_IRQS(5),
.EXTRA_CFG_WIDTH(8),
.DEV_EXTRA_CFG_WIDTH(19),
.LINK_MODE(LINK_MODE),
.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
) i_up_common (
.up_clk(s_axi_aclk),
@ -273,7 +275,12 @@ jesd204_up_common #(
/* 16 */ device_cfg_buffer_early_release,
/* 15-08 */ device_cfg_buffer_delay,
/* 00-07 */ device_cfg_lmfc_offset
})
}),
.status_synth_params0(status_synth_params0),
.status_synth_params1(status_synth_params1),
.status_synth_params2(status_synth_params2)
);
jesd204_up_sysref #(

3
library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
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@ -124,6 +124,9 @@ adi_add_bus "rx_status" "slave" \
{ "core_status_lane_latency" "lane_latency" } \
{ "core_status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
{ "core_status_err_statistics_cnt" "err_statistics_cnt" } \
{ "status_synth_params0" "synth_params0" } \
{ "status_synth_params1" "synth_params1" } \
{ "status_synth_params2" "synth_params2" } \
}
ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]

16
library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
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@ -112,7 +112,11 @@ module axi_jesd204_tx #(
output core_ctrl_manual_sync_request,
input [1:0] core_status_state,
input [NUM_LINKS-1:0] core_status_sync
input [NUM_LINKS-1:0] core_status_sync,
input [31:0] status_synth_params0,
input [31:0] status_synth_params1,
input [31:0] status_synth_params2
);
localparam PCORE_VERSION = 32'h00010561; // 1.04.a
@ -186,12 +190,9 @@ jesd204_up_common #(
.ID(ID),
.NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS),
.DATA_PATH_WIDTH_LOG2(DATA_PATH_WIDTH_LOG2),
.NUM_IRQS(5),
.EXTRA_CFG_WIDTH(11),
.DEV_EXTRA_CFG_WIDTH(10),
.MAX_OCTETS_PER_FRAME(10),
.LINK_MODE(LINK_MODE),
.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
) i_up_common (
.up_clk(s_axi_aclk),
@ -253,7 +254,12 @@ jesd204_up_common #(
/* 09 */ device_cfg_sysref_disable,
/* 08 */ device_cfg_sysref_oneshot,
/* 00-07 */ device_cfg_lmfc_offset
})
}),
.status_synth_params0(status_synth_params0),
.status_synth_params1(status_synth_params1),
.status_synth_params2(status_synth_params2)
);
jesd204_up_sysref #(

3
library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
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@ -114,6 +114,9 @@ adi_add_bus "tx_status" "slave" \
{ \
{ "core_status_state" "state" } \
{ "core_status_sync" "sync" } \
{ "status_synth_params0" "synth_params0" } \
{ "status_synth_params1" "synth_params1" } \
{ "status_synth_params2" "synth_params2" } \
}
adi_add_bus "tx_ctrl" "master" \

6
library/jesd204/interfaces/interfaces_ip.tcl
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@ -73,6 +73,9 @@ adi_if_ports input 32 data
adi_if_define "jesd204_tx_status"
adi_if_ports output 1 state
adi_if_ports output 1 sync
adi_if_ports output -1 synth_params0
adi_if_ports output -1 synth_params1
adi_if_ports output -1 synth_params2
adi_if_define "jesd204_tx_event"
adi_if_ports output 1 sysref_alignment_error
@ -111,6 +114,9 @@ adi_if_ports output -1 lane_ifs_ready
adi_if_ports output -1 lane_latency_ready
adi_if_ports output -1 lane_latency
adi_if_ports output -1 err_statistics_cnt
adi_if_ports output -1 synth_params0
adi_if_ports output -1 synth_params1
adi_if_ports output -1 synth_params2
adi_if_define "jesd204_rx_ilas_config"
adi_if_ports output -1 valid

22
library/jesd204/jesd204_rx/jesd204_rx.v
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@ -121,7 +121,11 @@ module jesd204_rx #(
output [NUM_LANES-1:0] status_lane_ifs_ready,
output [14*NUM_LANES-1:0] status_lane_latency,
output [3*NUM_LANES-1:0] status_lane_emb_state,
output [8*NUM_LANES-1:0] status_lane_frame_align_err_cnt
output [8*NUM_LANES-1:0] status_lane_frame_align_err_cnt,
output [31:0] status_synth_params0,
output [31:0] status_synth_params1,
output [31:0] status_synth_params2
);
/*
@ -600,5 +604,21 @@ end
endgenerate
// Core static parameters
assign status_synth_params0 = {NUM_LANES};
assign status_synth_params1 = {
/*31:16 */ 16'b0,
/*15: 8 */ 3'b0,TPL_DATA_PATH_WIDTH[4:0],
/* 7: 0 */ 4'b0,DPW_LOG2[3:0]};
assign status_synth_params2 = {
/*31:19 */ 13'b0,
/* 18 */ ENABLE_CHAR_REPLACE[0],
/* 17 */ ENABLE_FRAME_ALIGN_ERR_RESET[0],
/* 16 */ ENABLE_FRAME_ALIGN_CHECK[0],
/*15:13 */ 3'b0,
/* 12 */ ASYNC_CLK[0],
/*11:10 */ 2'b0,
/* 9: 8 */ LINK_MODE[1:0],
/* 7: 0 */ NUM_LINKS[7:0]};
endmodule

3
library/jesd204/jesd204_rx/jesd204_rx_ip.tcl
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@ -132,6 +132,9 @@ adi_add_bus "rx_status" "master" \
{ "status_lane_ifs_ready" "lane_ifs_ready" } \
{ "status_lane_latency" "lane_latency" } \
{ "status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
{ "status_synth_params0" "synth_params0" } \
{ "status_synth_params1" "synth_params1" } \
{ "status_synth_params2" "synth_params2" } \
}
adi_add_bus "rx_ilas_config" "master" \

20
library/jesd204/jesd204_tx/jesd204_tx.v
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@ -107,7 +107,11 @@ module jesd204_tx #(
output device_event_sysref_alignment_error,
output [NUM_LINKS-1:0] status_sync,
output [1:0] status_state
output [1:0] status_state,
output [31:0] status_synth_params0,
output [31:0] status_synth_params1,
output [31:0] status_synth_params2
);
@ -531,4 +535,18 @@ pipeline_stage #(
})
);
// Core static parameters
assign status_synth_params0 = {NUM_LANES};
assign status_synth_params1 = {
/*31:16 */ 16'b0,
/*15: 8 */ 3'b0,TPL_DATA_PATH_WIDTH[4:0],
/* 7: 0 */ 4'b0,DPW_LOG2[3:0]};
assign status_synth_params2 = {
/*31:16 */ 16'b0,
/*15:13 */ 3'b0,
/* 12 */ ASYNC_CLK[0],
/*11:10 */ 2'b0,
/* 9: 8 */ LINK_MODE[1:0],
/* 7: 0 */ NUM_LINKS[7:0]};
endmodule

3
library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
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@ -134,6 +134,9 @@ adi_add_bus "tx_status" "master" \
{ \
{ "status_state" "state" } \
{ "status_sync" "sync" } \
{ "status_synth_params0" "synth_params0" } \
{ "status_synth_params1" "synth_params1" } \
{ "status_synth_params2" "synth_params2" } \
}
adi_add_bus "tx_ctrl" "slave" \