From 71e14f64e63b6444a4db885c4ab64b80f2f6f3c8 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 10 May 2018 11:13:22 +0200 Subject: [PATCH] axi_dmac: Route destination request ID through the burst memory Currently the destination side request ID is synchronized response ID from the source side. This signal is effectively the same as the synchronized src ID inside the burst memory. The only difference is that they might not increment in the exact same clock cycle. Exporting the request ID from the burst memory means we can remove the extra synchronizer block. This has the added bonus that the request ID will increment in the same clock cycle as when the data becomes available from the memory. This means we can assume that when there is a outstanding burst request indicated via the ID that data is available from the memory and vice versa when data is available from the memory that there is a outstanding burst request. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac_burst_memory.v | 6 +++++- library/axi_dmac/axi_dmac_constr.ttcl | 2 +- library/axi_dmac/request_arb.v | 14 +++----------- 3 files changed, 9 insertions(+), 13 deletions(-) diff --git a/library/axi_dmac/axi_dmac_burst_memory.v b/library/axi_dmac/axi_dmac_burst_memory.v index 9ec373f2f..87f960224 100644 --- a/library/axi_dmac/axi_dmac_burst_memory.v +++ b/library/axi_dmac/axi_dmac_burst_memory.v @@ -53,7 +53,9 @@ module axi_dmac_burst_memory #( output dest_data_valid, input dest_data_ready, - output [DATA_WIDTH_DEST-1:0] dest_data + output [DATA_WIDTH_DEST-1:0] dest_data, + + output [ID_WIDTH-1:0] dest_request_id ); localparam DATA_WIDTH = DATA_WIDTH_SRC > DATA_WIDTH_DEST ? @@ -338,4 +340,6 @@ sync_bits #( .out (src_dest_id) ); +assign dest_request_id = dest_src_id; + endmodule diff --git a/library/axi_dmac/axi_dmac_constr.ttcl b/library/axi_dmac/axi_dmac_constr.ttcl index 556f9089d..061cec4c9 100644 --- a/library/axi_dmac/axi_dmac_constr.ttcl +++ b/library/axi_dmac/axi_dmac_constr.ttcl @@ -190,7 +190,7 @@ set_false_path -quiet \ -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] set_false_path -quiet \ -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ - -filter {name =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \ + -filter {name =~ *i_dest_sync_id* && IS_SEQUENTIAL}] \ -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] set_false_path -quiet \ -from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && IS_SEQUENTIAL}] \ diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index c60ec8304..f7d3deb6e 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -699,16 +699,6 @@ sync_bits #( .out(src_request_id) ); -sync_bits #( - .NUM_OF_BITS(ID_WIDTH), - .ASYNC_CLK(ASYNC_CLK_SRC_DEST) -) i_sync_dest_request_id ( - .out_clk(dest_clk), - .out_resetn(1'b1), - .in(src_response_id), - .out(dest_request_id) -); - sync_bits #( .NUM_OF_BITS(ID_WIDTH), .ASYNC_CLK(ASYNC_CLK_DEST_REQ) @@ -752,7 +742,9 @@ axi_dmac_burst_memory #( .dest_reset(~dest_resetn), .dest_data_valid(dest_fifo_valid), .dest_data_ready(dest_fifo_ready), - .dest_data(dest_fifo_data) + .dest_data(dest_fifo_data), + + .dest_request_id(dest_request_id) ); wire _dest_valid;