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axi_adc_decimate: Make adc_reset external

main
Adrian Costina 2017-03-29 11:12:23 +03:00 committed by Lars-Peter Clausen
parent 500112f79b
commit 7227e74444
4 changed files with 1 additions and 6 deletions
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2
library/axi_adc_decimate/axi_adc_decimate.v
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@ -40,6 +40,7 @@
module axi_adc_decimate(
input adc_clk,
input adc_rst,
input [15:0] adc_data_a,
input [15:0] adc_data_b,
@ -221,7 +222,6 @@ module axi_adc_decimate(
axi_adc_decimate_reg axi_adc_decimate_reg (
.clk (adc_clk),
.adc_rst (adc_rst),
.adc_decimation_ratio (decimation_ratio),
.adc_filter_mask (filter_mask),

1
library/axi_adc_decimate/axi_adc_decimate_constr.xdc
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@ -1,7 +1,6 @@
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]

1
library/axi_adc_decimate/axi_adc_decimate_ip.tcl
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@ -6,7 +6,6 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_adc_decimate
adi_ip_files axi_adc_decimate [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_adc_decimate_constr.xdc" \
"fir_decim.v" \

3
library/axi_adc_decimate/axi_adc_decimate_reg.v
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@ -40,7 +40,6 @@
module axi_adc_decimate_reg(
input clk,
output adc_rst,
output [31:0] adc_decimation_ratio,
output [31:0] adc_filter_mask,
@ -74,8 +73,6 @@ module axi_adc_decimate_reg(
assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
ad_rst i_core_rst_reg (.preset(~up_rstn), .clk(clk), .rst(adc_rst));
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;