altera additions and replacements
Rejeesh Kutty
parent
8deb36ce08
commit
724bd70a06
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@ -208,7 +208,7 @@ module axi_dmac_alt (
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [13:0] s_axi_awaddr;
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input [ 1:0] s_axi_awid;
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input [ 2:0] s_axi_awid;
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input [ 7:0] s_axi_awlen;
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input [ 2:0] s_axi_awsize;
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input [ 1:0] s_axi_awburst;
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@ -223,11 +223,11 @@ module axi_dmac_alt (
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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output [ 1:0] s_axi_bid;
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output [ 2:0] s_axi_bid;
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input s_axi_bready;
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input s_axi_arvalid;
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input [13:0] s_axi_araddr;
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input [ 1:0] s_axi_arid;
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input [ 2:0] s_axi_arid;
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input [ 7:0] s_axi_arlen;
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input [ 2:0] s_axi_arsize;
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input [ 1:0] s_axi_arburst;
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@ -238,7 +238,7 @@ module axi_dmac_alt (
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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output [ 1:0] s_axi_rid;
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output [ 2:0] s_axi_rid;
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output s_axi_rlast;
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input s_axi_rready;
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@ -248,7 +248,7 @@ module axi_dmac_alt (
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input m_dest_axi_aresetn;
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output m_dest_axi_awvalid;
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output [31:0] m_dest_axi_awaddr;
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output [ 1:0] m_dest_axi_awid;
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output [ 2:0] m_dest_axi_awid;
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output [ 7:0] m_dest_axi_awlen;
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output [ 2:0] m_dest_axi_awsize;
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output [ 1:0] m_dest_axi_awburst;
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@ -263,11 +263,11 @@ module axi_dmac_alt (
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input m_dest_axi_wready;
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input m_dest_axi_bvalid;
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input [ 1:0] m_dest_axi_bresp;
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input [ 1:0] m_dest_axi_bid;
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input [ 2:0] m_dest_axi_bid;
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output m_dest_axi_bready;
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output m_dest_axi_arvalid;
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output [31:0] m_dest_axi_araddr;
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output [ 1:0] m_dest_axi_arid;
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output [ 2:0] m_dest_axi_arid;
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output [ 7:0] m_dest_axi_arlen;
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output [ 2:0] m_dest_axi_arsize;
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output [ 1:0] m_dest_axi_arburst;
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@ -278,7 +278,7 @@ module axi_dmac_alt (
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input m_dest_axi_rvalid;
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input [ 1:0] m_dest_axi_rresp;
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input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata;
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input [ 1:0] m_dest_axi_rid;
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input [ 2:0] m_dest_axi_rid;
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input m_dest_axi_rlast;
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output m_dest_axi_rready;
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@ -288,7 +288,7 @@ module axi_dmac_alt (
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input m_src_axi_aresetn;
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output m_src_axi_awvalid;
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output [31:0] m_src_axi_awaddr;
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output [ 1:0] m_src_axi_awid;
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output [ 2:0] m_src_axi_awid;
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output [ 7:0] m_src_axi_awlen;
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output [ 2:0] m_src_axi_awsize;
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output [ 1:0] m_src_axi_awburst;
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@ -303,11 +303,11 @@ module axi_dmac_alt (
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input m_src_axi_wready;
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input m_src_axi_bvalid;
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input [ 1:0] m_src_axi_bresp;
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input [ 1:0] m_src_axi_bid;
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input [ 2:0] m_src_axi_bid;
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output m_src_axi_bready;
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output m_src_axi_arvalid;
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output [31:0] m_src_axi_araddr;
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output [ 1:0] m_src_axi_arid;
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output [ 2:0] m_src_axi_arid;
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output [ 7:0] m_src_axi_arlen;
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output [ 2:0] m_src_axi_arsize;
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output [ 1:0] m_src_axi_arburst;
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@ -318,7 +318,7 @@ module axi_dmac_alt (
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input m_src_axi_rvalid;
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input [ 1:0] m_src_axi_rresp;
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input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata;
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input [ 1:0] m_src_axi_rid;
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input [ 2:0] m_src_axi_rid;
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input m_src_axi_rlast;
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output m_src_axi_rready;
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@ -349,8 +349,8 @@ module axi_dmac_alt (
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// defaults
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assign s_axi_bid = 2'd0;
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assign s_axi_rid = 2'd0;
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assign s_axi_bid = 3'd0;
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assign s_axi_rid = 3'd0;
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assign s_axi_rlast = 1'd0;
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// instantiation
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@ -19,6 +19,8 @@ add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/commo
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add_fileset_file axi_fifo.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/axi_fifo.v
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add_fileset_file address_gray.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/address_gray.v
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add_fileset_file address_gray_pipelined.v VERILOG PATH $ad_hdl_dir/library/axi_fifo/address_gray_pipelined.v
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add_fileset_file inc_id.h VERILOG_INCLUDE PATH inc_id.h
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add_fileset_file resp.h VERILOG_INCLUDE PATH resp.h
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add_fileset_file address_generator.v VERILOG PATH address_generator.v
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add_fileset_file data_mover.v VERILOG PATH data_mover.v
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add_fileset_file request_arb.v VERILOG PATH request_arb.v
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@ -36,6 +38,7 @@ add_fileset_file splitter.v VERILOG PATH splitter.v
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add_fileset_file response_generator.v VERILOG PATH response_generator.v
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add_fileset_file axi_dmac.v VERILOG PATH axi_dmac.v
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add_fileset_file axi_repack.v VERILOG PATH axi_repack.v
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add_fileset_file axi_dmac_alt.v VERILOG PATH axi_dmac_alt.v
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# parameters
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@ -173,7 +176,7 @@ add_interface_port s_axi s_axi_rvalid rvalid Output 1
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add_interface_port s_axi s_axi_rresp rresp Output 2
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add_interface_port s_axi s_axi_rdata rdata Output 32
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add_interface_port s_axi s_axi_rready rready Input 1
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add_interface_port s_axi s_axi_awid awid Input 2
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add_interface_port s_axi s_axi_awid awid Input 3
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add_interface_port s_axi s_axi_awlen awlen Input 8
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add_interface_port s_axi s_axi_awsize awsize Input 3
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add_interface_port s_axi s_axi_awburst awburst Input 2
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@ -181,15 +184,15 @@ add_interface_port s_axi s_axi_awlock awlock Input 1
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add_interface_port s_axi s_axi_awcache awcache Input 4
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add_interface_port s_axi s_axi_awprot awprot Input 3
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add_interface_port s_axi s_axi_wlast wlast Input 1
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add_interface_port s_axi s_axi_bid bid Output 2
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add_interface_port s_axi s_axi_arid arid Input 2
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add_interface_port s_axi s_axi_bid bid Output 3
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add_interface_port s_axi s_axi_arid arid Input 3
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add_interface_port s_axi s_axi_arlen arlen Input 8
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add_interface_port s_axi s_axi_arsize arsize Input 3
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add_interface_port s_axi s_axi_arburst arburst Input 2
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add_interface_port s_axi s_axi_arlock arlock Input 1
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add_interface_port s_axi s_axi_arcache arcache Input 4
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add_interface_port s_axi s_axi_arprot arprot Input 3
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add_interface_port s_axi s_axi_rid rid Output 2
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add_interface_port s_axi s_axi_rid rid Output 3
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add_interface_port s_axi s_axi_rlast rlast Output 1
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# conditional interface
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@ -227,7 +230,7 @@ proc axi_dmac_elaborate {} {
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add_interface_port m_dest_axi m_dest_axi_rresp rresp Input 2
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add_interface_port m_dest_axi m_dest_axi_rdata rdata Input C_DMA_DATA_WIDTH_DEST
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add_interface_port m_dest_axi m_dest_axi_rready rready Output 1
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add_interface_port m_dest_axi m_dest_axi_awid awid Output 2
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add_interface_port m_dest_axi m_dest_axi_awid awid Output 3
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add_interface_port m_dest_axi m_dest_axi_awlen awlen Output 8
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add_interface_port m_dest_axi m_dest_axi_awsize awsize Output 3
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add_interface_port m_dest_axi m_dest_axi_awburst awburst Output 2
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@ -235,15 +238,15 @@ proc axi_dmac_elaborate {} {
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add_interface_port m_dest_axi m_dest_axi_awcache awcache Output 4
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add_interface_port m_dest_axi m_dest_axi_awprot awprot Output 3
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add_interface_port m_dest_axi m_dest_axi_wlast wlast Output 1
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add_interface_port m_dest_axi m_dest_axi_bid bid Input 2
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add_interface_port m_dest_axi m_dest_axi_arid arid Output 2
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add_interface_port m_dest_axi m_dest_axi_bid bid Input 3
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add_interface_port m_dest_axi m_dest_axi_arid arid Output 3
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add_interface_port m_dest_axi m_dest_axi_arlen arlen Output 8
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add_interface_port m_dest_axi m_dest_axi_arsize arsize Output 3
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add_interface_port m_dest_axi m_dest_axi_arburst arburst Output 2
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add_interface_port m_dest_axi m_dest_axi_arlock arlock Output 1
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add_interface_port m_dest_axi m_dest_axi_arcache arcache Output 4
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add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3
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add_interface_port m_dest_axi m_dest_axi_rid rid Input 2
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add_interface_port m_dest_axi m_dest_axi_rid rid Input 3
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add_interface_port m_dest_axi m_dest_axi_rlast rlast Input 1
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}
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@ -276,7 +279,7 @@ proc axi_dmac_elaborate {} {
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add_interface_port m_src_axi m_src_axi_rresp rresp Input 2
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add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC
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add_interface_port m_src_axi m_src_axi_rready rready Output 1
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add_interface_port m_src_axi m_src_axi_awid awid Output 2
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add_interface_port m_src_axi m_src_axi_awid awid Output 3
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add_interface_port m_src_axi m_src_axi_awlen awlen Output 8
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add_interface_port m_src_axi m_src_axi_awsize awsize Output 3
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add_interface_port m_src_axi m_src_axi_awburst awburst Output 2
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@ -284,15 +287,15 @@ proc axi_dmac_elaborate {} {
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add_interface_port m_src_axi m_src_axi_awcache awcache Output 4
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add_interface_port m_src_axi m_src_axi_awprot awprot Output 3
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add_interface_port m_src_axi m_src_axi_wlast wlast Output 1
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add_interface_port m_src_axi m_src_axi_bid bid Input 2
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add_interface_port m_src_axi m_src_axi_arid arid Output 2
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add_interface_port m_src_axi m_src_axi_bid bid Input 3
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add_interface_port m_src_axi m_src_axi_arid arid Output 3
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add_interface_port m_src_axi m_src_axi_arlen arlen Output 8
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add_interface_port m_src_axi m_src_axi_arsize arsize Output 3
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add_interface_port m_src_axi m_src_axi_arburst arburst Output 2
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add_interface_port m_src_axi m_src_axi_arlock arlock Output 1
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add_interface_port m_src_axi m_src_axi_arcache arcache Output 4
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add_interface_port m_src_axi m_src_axi_arprot arprot Output 3
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add_interface_port m_src_axi m_src_axi_rid rid Input 2
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add_interface_port m_src_axi m_src_axi_rid rid Input 3
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add_interface_port m_src_axi m_src_axi_rlast rlast Input 1
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}
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@ -0,0 +1,99 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_jesd_align (
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// jesd interface
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rx_clk,
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rx_sof,
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rx_ip_data,
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rx_data);
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// jesd interface
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input rx_clk;
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input [ 3:0] rx_sof;
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input [31:0] rx_ip_data;
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// aligned data
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output [31:0] rx_data;
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// internal registers
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reg [31:0] rx_ip_data_d = 'd0;
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reg [31:0] rx_data = 'd0;
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// dword may contain more than one frame per clock
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always @(posedge rx_clk) begin
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rx_ip_data_d <= rx_ip_data;
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if (rx_sof[3] == 1'b1) begin
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rx_data[31:24] <= rx_ip_data[ 7: 0];
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rx_data[23:16] <= rx_ip_data[15: 8];
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rx_data[15: 8] <= rx_ip_data[23:16];
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rx_data[ 7: 0] <= rx_ip_data[31:24];
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end else if (rx_sof[2] == 1'b1) begin
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rx_data[31:24] <= rx_ip_data[31:24];
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rx_data[23:16] <= rx_ip_data_d[ 7: 0];
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rx_data[15: 8] <= rx_ip_data_d[15: 8];
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rx_data[ 7: 0] <= rx_ip_data_d[23:16];
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end else if (rx_sof[1] == 1'b1) begin
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rx_data[31:24] <= rx_ip_data[23:16];
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rx_data[23:16] <= rx_ip_data[31:24];
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rx_data[15: 8] <= rx_ip_data_d[ 7: 0];
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rx_data[ 7: 0] <= rx_ip_data_d[15: 8];
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end else if (rx_sof[0] == 1'b1) begin
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rx_data[31:24] <= rx_ip_data[15: 8];
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rx_data[23:16] <= rx_ip_data[23:16];
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rx_data[15: 8] <= rx_ip_data[31:24];
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rx_data[ 7: 0] <= rx_ip_data_d[ 7: 0];
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end else begin
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rx_data[31:24] <= 8'd0;
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rx_data[23:16] <= 8'd0;
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rx_data[15: 8] <= 8'd0;
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rx_data[ 7: 0] <= 8'd0;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,68 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
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// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
|
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// contributors may be used to endorse or promote products derived
|
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// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
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// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
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// - Use of the software either in source or binary form, must be run
|
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// on or directly connected to an Analog Devices Inc. component.
|
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//
|
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
|
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_rst (
|
||||
|
||||
// clock reset
|
||||
|
||||
preset,
|
||||
clk,
|
||||
rst);
|
||||
|
||||
// clock reset
|
||||
|
||||
input preset;
|
||||
input clk;
|
||||
output rst;
|
||||
|
||||
// simple reset gen
|
||||
|
||||
lpm_ff #(.LPM_WIDTH(1), .LPM_AVALUE(1'b1)) i_rst_reg (
|
||||
.enable (1'b1),
|
||||
.data (1'b0),
|
||||
.aset (preset),
|
||||
.clock (clk),
|
||||
.q (rst));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -0,0 +1,266 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module ad_xcvr_rx_rst (
|
||||
|
||||
// clock, reset and pll locked
|
||||
|
||||
rx_clk,
|
||||
rx_rstn,
|
||||
rx_sw_rstn,
|
||||
rx_pll_locked,
|
||||
|
||||
// xcvr status and reset
|
||||
|
||||
rx_cal_busy,
|
||||
rx_cdr_locked,
|
||||
rx_analog_reset,
|
||||
rx_digital_reset,
|
||||
rx_ready,
|
||||
rx_rst_state);
|
||||
|
||||
// parameters
|
||||
|
||||
parameter NUM_OF_LANES = 4;
|
||||
parameter RX_CAL_DONE_COUNT_WIDTH = 8;
|
||||
parameter RX_CDR_LOCKED_COUNT_WIDTH = 8;
|
||||
parameter RX_ANALOG_RESET_COUNT_WIDTH = 5;
|
||||
parameter RX_DIGITAL_RESET_COUNT_WIDTH = 12;
|
||||
|
||||
localparam RX_RESET_FSM_INIT = 4'h0;
|
||||
localparam RX_RESET_FSM_ARST0 = 4'h1;
|
||||
localparam RX_RESET_FSM_ARST1 = 4'h2;
|
||||
localparam RX_RESET_FSM_ARST2 = 4'h3;
|
||||
localparam RX_RESET_FSM_ARST3 = 4'h4;
|
||||
localparam RX_RESET_FSM_ARSTD = 4'h5;
|
||||
localparam RX_RESET_FSM_DRST0 = 4'h6;
|
||||
localparam RX_RESET_FSM_DRST1 = 4'h7;
|
||||
localparam RX_RESET_FSM_DRST2 = 4'h8;
|
||||
localparam RX_RESET_FSM_DRST3 = 4'h9;
|
||||
localparam RX_RESET_FSM_DRSTD = 4'ha;
|
||||
localparam RX_RESET_FSM_IDLE = 4'hb;
|
||||
|
||||
// clock, reset and pll locked
|
||||
|
||||
input rx_clk;
|
||||
input rx_rstn;
|
||||
input rx_sw_rstn;
|
||||
input rx_pll_locked;
|
||||
|
||||
// xcvr status and reset
|
||||
|
||||
input [NUM_OF_LANES-1:0] rx_cal_busy;
|
||||
input [NUM_OF_LANES-1:0] rx_cdr_locked;
|
||||
output [NUM_OF_LANES-1:0] rx_analog_reset;
|
||||
output [NUM_OF_LANES-1:0] rx_digital_reset;
|
||||
output rx_ready;
|
||||
output [ 3:0] rx_rst_state;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 2:0] rx_rst_req_m = 'd0;
|
||||
reg rx_rst_req = 'd0;
|
||||
reg [RX_CAL_DONE_COUNT_WIDTH:0] rx_cal_done_cnt = 'd0;
|
||||
reg [RX_CDR_LOCKED_COUNT_WIDTH:0] rx_cdr_locked_cnt = 'd0;
|
||||
reg [RX_ANALOG_RESET_COUNT_WIDTH:0] rx_analog_reset_cnt = 'd0;
|
||||
reg [RX_DIGITAL_RESET_COUNT_WIDTH:0] rx_digital_reset_cnt = 'd0;
|
||||
reg [ 3:0] rx_rst_state = 'd0;
|
||||
reg [NUM_OF_LANES-1:0] rx_analog_reset = 'd0;
|
||||
reg [NUM_OF_LANES-1:0] rx_digital_reset = 'd0;
|
||||
reg rx_ready = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire rx_rst_req_s;
|
||||
wire rx_cal_busy_s;
|
||||
wire rx_cal_done_s;
|
||||
wire rx_cal_done_valid_s;
|
||||
wire rx_cdr_locked_s;
|
||||
wire rx_cdr_locked_valid_s;
|
||||
wire rx_analog_reset_s;
|
||||
wire rx_analog_reset_valid_s;
|
||||
wire rx_digital_reset_s;
|
||||
wire rx_digital_reset_valid_s;
|
||||
|
||||
// reset request
|
||||
|
||||
assign rx_rst_req_s = ~(rx_rstn & rx_sw_rstn & rx_pll_locked);
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
rx_rst_req_m <= {rx_rst_req_m[1:0], rx_rst_req_s};
|
||||
rx_rst_req <= rx_rst_req_m[2];
|
||||
end
|
||||
|
||||
// cal busy check width
|
||||
|
||||
assign rx_cal_busy_s = | rx_cal_busy;
|
||||
assign rx_cal_done_s = ~rx_cal_busy_s;
|
||||
assign rx_cal_done_valid_s = rx_cal_done_cnt[RX_CAL_DONE_COUNT_WIDTH];
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
if (rx_cal_done_s == 1'd0) begin
|
||||
rx_cal_done_cnt <= 'd0;
|
||||
end else if (rx_cal_done_cnt[RX_CAL_DONE_COUNT_WIDTH] == 1'b0) begin
|
||||
rx_cal_done_cnt <= rx_cal_done_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// cdr locked check width
|
||||
|
||||
assign rx_cdr_locked_s = | rx_cdr_locked;
|
||||
assign rx_cdr_locked_valid_s = rx_cdr_locked_cnt[RX_CDR_LOCKED_COUNT_WIDTH];
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
if (rx_cdr_locked_s == 1'd0) begin
|
||||
rx_cdr_locked_cnt <= 'd0;
|
||||
end else if (rx_cdr_locked_cnt[RX_CDR_LOCKED_COUNT_WIDTH] == 1'b0) begin
|
||||
rx_cdr_locked_cnt <= rx_cdr_locked_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// analog reset width
|
||||
|
||||
assign rx_analog_reset_s = | rx_analog_reset;
|
||||
assign rx_analog_reset_valid_s = rx_analog_reset_cnt[RX_ANALOG_RESET_COUNT_WIDTH];
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
if (rx_analog_reset_s == 1'd0) begin
|
||||
rx_analog_reset_cnt <= 'd0;
|
||||
end else if (rx_analog_reset_cnt[RX_ANALOG_RESET_COUNT_WIDTH] == 1'b0) begin
|
||||
rx_analog_reset_cnt <= rx_analog_reset_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// digital reset width
|
||||
|
||||
assign rx_digital_reset_s = | rx_digital_reset;
|
||||
assign rx_digital_reset_valid_s = rx_digital_reset_cnt[RX_DIGITAL_RESET_COUNT_WIDTH];
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
if (rx_digital_reset_s == 1'd0) begin
|
||||
rx_digital_reset_cnt <= 'd0;
|
||||
end else if (rx_digital_reset_cnt[RX_DIGITAL_RESET_COUNT_WIDTH] == 1'b0) begin
|
||||
rx_digital_reset_cnt <= rx_digital_reset_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// state machine
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
if (rx_rst_req == 1'b1) begin
|
||||
rx_rst_state <= RX_RESET_FSM_INIT;
|
||||
end else begin
|
||||
case (rx_rst_state)
|
||||
RX_RESET_FSM_INIT: begin
|
||||
rx_rst_state <= RX_RESET_FSM_ARST0;
|
||||
end
|
||||
RX_RESET_FSM_ARST0: begin
|
||||
if ((rx_cal_done_valid_s == 1'b1) && (rx_analog_reset_valid_s == 1'b1)) begin
|
||||
rx_rst_state <= RX_RESET_FSM_ARST1;
|
||||
end else begin
|
||||
rx_rst_state <= RX_RESET_FSM_ARST0;
|
||||
end
|
||||
end
|
||||
RX_RESET_FSM_ARST1: begin
|
||||
rx_rst_state <= RX_RESET_FSM_ARST2;
|
||||
end
|
||||
RX_RESET_FSM_ARST2: begin
|
||||
rx_rst_state <= RX_RESET_FSM_ARST3;
|
||||
end
|
||||
RX_RESET_FSM_ARST3: begin
|
||||
rx_rst_state <= RX_RESET_FSM_ARSTD;
|
||||
end
|
||||
RX_RESET_FSM_ARSTD: begin
|
||||
rx_rst_state <= RX_RESET_FSM_DRST0;
|
||||
end
|
||||
RX_RESET_FSM_DRST0: begin
|
||||
if ((rx_cdr_locked_valid_s == 1'b1) && (rx_digital_reset_valid_s == 1'b1)) begin
|
||||
rx_rst_state <= RX_RESET_FSM_DRST1;
|
||||
end else begin
|
||||
rx_rst_state <= RX_RESET_FSM_DRST0;
|
||||
end
|
||||
end
|
||||
RX_RESET_FSM_DRST1: begin
|
||||
rx_rst_state <= RX_RESET_FSM_DRST2;
|
||||
end
|
||||
RX_RESET_FSM_DRST2: begin
|
||||
rx_rst_state <= RX_RESET_FSM_DRST3;
|
||||
end
|
||||
RX_RESET_FSM_DRST3: begin
|
||||
rx_rst_state <= RX_RESET_FSM_DRSTD;
|
||||
end
|
||||
RX_RESET_FSM_DRSTD: begin
|
||||
rx_rst_state <= RX_RESET_FSM_IDLE;
|
||||
end
|
||||
RX_RESET_FSM_IDLE: begin
|
||||
rx_rst_state <= RX_RESET_FSM_IDLE;
|
||||
end
|
||||
default: begin
|
||||
rx_rst_state <= RX_RESET_FSM_INIT;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
// output signals
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
if (rx_rst_state == RX_RESET_FSM_INIT) begin
|
||||
rx_analog_reset <= {{NUM_OF_LANES{1'b1}}};
|
||||
end else if (rx_rst_state == RX_RESET_FSM_ARSTD) begin
|
||||
rx_analog_reset <= {{NUM_OF_LANES{1'b0}}};
|
||||
end
|
||||
if (rx_rst_state == RX_RESET_FSM_INIT) begin
|
||||
rx_digital_reset <= {{NUM_OF_LANES{1'b1}}};
|
||||
end else if (rx_rst_state == RX_RESET_FSM_DRSTD) begin
|
||||
rx_digital_reset <= {{NUM_OF_LANES{1'b0}}};
|
||||
end
|
||||
if (rx_rst_state == RX_RESET_FSM_IDLE) begin
|
||||
rx_ready <= 1'b1;
|
||||
end else begin
|
||||
rx_ready <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue