axi_ad9963: Allow to disable the IDELAYs on the ADC data path
Not all designs need the IDELAYs. Disabling them can reduce power consumption of the system. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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09ffe42603
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72cdd846b0
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@ -43,6 +43,7 @@ module axi_ad9963 #(
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parameter ID = 0,
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parameter DEVICE_TYPE = 0,
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parameter ADC_IODELAY_ENABLE = 0,
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parameter DAC_IODELAY_ENABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group",
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parameter DAC_DATAPATH_DISABLE = 0,
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@ -176,6 +177,7 @@ module axi_ad9963 #(
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axi_ad9963_if #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE),
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.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IO_DELAY_GROUP (IO_DELAY_GROUP))
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i_dev_if (
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@ -206,8 +208,9 @@ module axi_ad9963 #(
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axi_ad9963_rx #(
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.ID (ID),
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.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
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i_rx (
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.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE),
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.IODELAY_ENABLE (ADC_IODELAY_ENABLE)
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) i_rx (
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.adc_rst (adc_rst),
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.adc_clk (adc_clk),
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.adc_valid (adc_valid_s),
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@ -36,6 +36,7 @@ module axi_ad9963_if #(
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parameter DEVICE_TYPE = 0,
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parameter DAC_IODELAY_ENABLE = 0,
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parameter ADC_IODELAY_ENABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group") (
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// physical interface (receive)
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@ -135,6 +136,7 @@ module axi_ad9963_if #(
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ad_lvds_in #(
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.SINGLE_ENDED (1),
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.DEVICE_TYPE (DEVICE_TYPE),
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.IODELAY_ENABLE (ADC_IODELAY_ENABLE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_rx_data (
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@ -158,6 +160,7 @@ module axi_ad9963_if #(
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ad_lvds_in #(
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.SINGLE_ENDED (1),
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.DEVICE_TYPE (DEVICE_TYPE),
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.IODELAY_ENABLE (ADC_IODELAY_ENABLE),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_rx_iq (
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@ -42,6 +42,7 @@ module axi_ad9963_rx #(
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// parameters
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parameter DATAPATH_DISABLE = 0,
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parameter IODELAY_ENABLE = 0,
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parameter ID = 0) (
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// adc interface
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@ -233,6 +234,8 @@ module axi_ad9963_rx #(
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// adc delay control
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generate if (IODELAY_ENABLE == 1) begin
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up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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@ -251,6 +254,16 @@ module axi_ad9963_rx #(
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.up_rdata (up_rdata_s[3]),
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.up_rack (up_rack_s[3]));
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end else begin
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assign up_dld = 'h00;
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assign up_dwdata = 'h00;
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assign delay_rst = 1'b1;
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assign up_wack_s[3] = 0;
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assign up_rack_s[3] = 0;
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assign up_rdata_s[3] = 'h00;
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end
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endgenerate
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endmodule
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// ***************************************************************************
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