zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

adrv9001/zcu102: Update interface signal names based on direction 

Let the names of signals from source synchronous interface match the
direction of the signals.
main
Laszlo Nagy 2020-08-25 08:17:35 +01:00 committed by Laszlo Nagy
parent a212ad6e58
commit 72f916fcf5
4 changed files with 162 additions and 162 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

80
projects/adrv9001/zcu102/cmos_constr.xdc
View File

@ -1,51 +1,51 @@
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_out_n] ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_out_p] ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_out_n] ;## FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_out_p] ;## FMC_HPC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18 } [get_ports rx1_qdata_out_n] ;## FMC_HPC0_LA04_N IO_L21N_T3L_N5_AD8N_66
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 } [get_ports rx1_qdata_out_p] ;## FMC_HPC0_LA04_P IO_L21P_T3L_N4_AD8P_66
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18 } [get_ports rx1_strobe_out_n] ;## FMC_HPC0_LA02_N IO_L23N_T3U_N9_66
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18 } [get_ports rx1_strobe_out_p] ;## FMC_HPC0_LA02_P IO_L23P_T3U_N8_66
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_in_n] ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS18 } [get_ports rx1_dclk_in_p] ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_in_n] ;## FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 } [get_ports rx1_idata_in_p] ;## FMC_HPC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVCMOS18 } [get_ports rx1_qdata_in_n] ;## FMC_HPC0_LA04_N IO_L21N_T3L_N5_AD8N_66
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 } [get_ports rx1_qdata_in_p] ;## FMC_HPC0_LA04_P IO_L21P_T3L_N4_AD8P_66
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18 } [get_ports rx1_strobe_in_n] ;## FMC_HPC0_LA02_N IO_L23N_T3U_N9_66
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18 } [get_ports rx1_strobe_in_p] ;## FMC_HPC0_LA02_P IO_L23P_T3U_N8_66
set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports rx2_dclk_out_n] ;## FMC_HPC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports rx2_dclk_out_p] ;## FMC_HPC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports rx2_idata_out_n] ;## FMC_HPC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67
set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx2_idata_out_p] ;## FMC_HPC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports rx2_qdata_out_n] ;## FMC_HPC0_LA19_N IO_L23N_T3U_N9_67
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 } [get_ports rx2_qdata_out_p] ;## FMC_HPC0_LA19_P IO_L23P_T3U_N8_67
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 } [get_ports rx2_strobe_out_n] ;## FMC_HPC0_LA21_N IO_L21N_T3L_N5_AD8N_67
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports rx2_strobe_out_p] ;## FMC_HPC0_LA21_P IO_L21P_T3L_N4_AD8P_67
set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18 } [get_ports rx2_dclk_in_n] ;## FMC_HPC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports rx2_dclk_in_p] ;## FMC_HPC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports rx2_idata_in_n] ;## FMC_HPC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67
set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx2_idata_in_p] ;## FMC_HPC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports rx2_qdata_in_n] ;## FMC_HPC0_LA19_N IO_L23N_T3U_N9_67
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 } [get_ports rx2_qdata_in_p] ;## FMC_HPC0_LA19_P IO_L23P_T3U_N8_67
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18 } [get_ports rx2_strobe_in_n] ;## FMC_HPC0_LA21_N IO_L21N_T3L_N5_AD8N_67
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports rx2_strobe_in_p] ;## FMC_HPC0_LA21_P IO_L21P_T3L_N4_AD8P_67
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_in_n] ;## FMC_HPC0_LA07_N IO_L18N_T2U_N11_AD2N_66
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_in_p] ;## FMC_HPC0_LA07_P IO_L18P_T2U_N10_AD2P_66
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_out_n] ;## FMC_HPC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_out_p] ;## FMC_HPC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 } [get_ports tx1_idata_in_n] ;## FMC_HPC0_LA08_N IO_L17N_T2U_N9_AD10N_66
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 } [get_ports tx1_idata_in_p] ;## FMC_HPC0_LA08_P IO_L17P_T2U_N8_AD10P_66
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 } [get_ports tx1_qdata_in_n] ;## FMC_HPC0_LA05_N IO_L20N_T3L_N3_AD1N_66
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18 } [get_ports tx1_qdata_in_p] ;## FMC_HPC0_LA05_P IO_L20P_T3L_N2_AD1P_66
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 } [get_ports tx1_strobe_in_n] ;## FMC_HPC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 } [get_ports tx1_strobe_in_p] ;## FMC_HPC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_out_n] ;## FMC_HPC0_LA07_N IO_L18N_T2U_N11_AD2N_66
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_out_p] ;## FMC_HPC0_LA07_P IO_L18P_T2U_N10_AD2P_66
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_in_n] ;## FMC_HPC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18 } [get_ports tx1_dclk_in_p] ;## FMC_HPC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 } [get_ports tx1_idata_out_n] ;## FMC_HPC0_LA08_N IO_L17N_T2U_N9_AD10N_66
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 } [get_ports tx1_idata_out_p] ;## FMC_HPC0_LA08_P IO_L17P_T2U_N8_AD10P_66
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 } [get_ports tx1_qdata_out_n] ;## FMC_HPC0_LA05_N IO_L20N_T3L_N3_AD1N_66
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVCMOS18 } [get_ports tx1_qdata_out_p] ;## FMC_HPC0_LA05_P IO_L20P_T3L_N2_AD1P_66
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 } [get_ports tx1_strobe_out_n] ;## FMC_HPC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 } [get_ports tx1_strobe_out_p] ;## FMC_HPC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_in_n] ;## FMC_HPC0_LA22_N IO_L20N_T3L_N3_AD1N_67
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_in_p] ;## FMC_HPC0_LA22_P IO_L20P_T3L_N2_AD1P_67
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_out_n] ;## FMC_HPC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_out_p] ;## FMC_HPC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18 } [get_ports tx2_idata_in_n] ;## FMC_HPC0_LA23_N IO_L19N_T3L_N1_DBC_AD9N_67
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18 } [get_ports tx2_idata_in_p] ;## FMC_HPC0_LA23_P IO_L19P_T3L_N0_DBC_AD9P_67
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18 } [get_ports tx2_qdata_in_n] ;## FMC_HPC0_LA25_N IO_L17N_T2U_N9_AD10N_67
set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18 } [get_ports tx2_qdata_in_p] ;## FMC_HPC0_LA25_P IO_L17P_T2U_N8_AD10P_67
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18 } [get_ports tx2_strobe_in_n] ;## FMC_HPC0_LA24_N IO_L18N_T2U_N11_AD2N_67
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 } [get_ports tx2_strobe_in_p] ;## FMC_HPC0_LA24_P IO_L18P_T2U_N10_AD2P_67
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_out_n] ;## FMC_HPC0_LA22_N IO_L20N_T3L_N3_AD1N_67
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_out_p] ;## FMC_HPC0_LA22_P IO_L20P_T3L_N2_AD1P_67
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_in_n] ;## FMC_HPC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18 } [get_ports tx2_dclk_in_p] ;## FMC_HPC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18 } [get_ports tx2_idata_out_n] ;## FMC_HPC0_LA23_N IO_L19N_T3L_N1_DBC_AD9N_67
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18 } [get_ports tx2_idata_out_p] ;## FMC_HPC0_LA23_P IO_L19P_T3L_N0_DBC_AD9P_67
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18 } [get_ports tx2_qdata_out_n] ;## FMC_HPC0_LA25_N IO_L17N_T2U_N9_AD10N_67
set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18 } [get_ports tx2_qdata_out_p] ;## FMC_HPC0_LA25_P IO_L17P_T2U_N8_AD10P_67
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18 } [get_ports tx2_strobe_out_n] ;## FMC_HPC0_LA24_N IO_L18N_T2U_N11_AD2N_67
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 } [get_ports tx2_strobe_out_p] ;## FMC_HPC0_LA24_P IO_L18P_T2U_N10_AD2P_67
# clocks
create_clock -name ref_clk -period 25.00 [get_ports fpga_ref_clk_p]
create_clock -name rx1_dclk_out -period 12.5 [get_ports rx1_dclk_out_p]
create_clock -name rx2_dclk_out -period 12.5 [get_ports rx2_dclk_out_p]
create_clock -name tx1_dclk_out -period 12.5 [get_ports tx1_dclk_out_p]
create_clock -name tx2_dclk_out -period 12.5 [get_ports tx2_dclk_out_p]
create_clock -name rx1_dclk_out -period 12.5 [get_ports rx1_dclk_in_p]
create_clock -name rx2_dclk_out -period 12.5 [get_ports rx2_dclk_in_p]
create_clock -name tx1_dclk_out -period 12.5 [get_ports tx1_dclk_in_p]
create_clock -name tx2_dclk_out -period 12.5 [get_ports tx2_dclk_in_p]
set_clock_latency -source -early 2 [get_clocks rx1_dclk_out]
set_clock_latency -source -early 2 [get_clocks rx2_dclk_out]

80
projects/adrv9001/zcu102/lvds_constr.xdc
View File

@ -1,51 +1,51 @@
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_out_n] ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_out_p] ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_idata_out_n] ;## FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_idata_out_p] ;## FMC_HPC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_qdata_out_n] ;## FMC_HPC0_LA04_N IO_L21N_T3L_N5_AD8N_66
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_qdata_out_p] ;## FMC_HPC0_LA04_P IO_L21P_T3L_N4_AD8P_66
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_strobe_out_n] ;## FMC_HPC0_LA02_N IO_L23N_T3U_N9_66
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_strobe_out_p] ;## FMC_HPC0_LA02_P IO_L23P_T3U_N8_66
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_in_n] ;## FMC_HPC0_LA00_CC_N IO_L13N_T2L_N1_GC_QBC_66
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_dclk_in_p] ;## FMC_HPC0_LA00_CC_P IO_L13P_T2L_N0_GC_QBC_66
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_idata_in_n] ;## FMC_HPC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_idata_in_p] ;## FMC_HPC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_qdata_in_n] ;## FMC_HPC0_LA04_N IO_L21N_T3L_N5_AD8N_66
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_qdata_in_p] ;## FMC_HPC0_LA04_P IO_L21P_T3L_N4_AD8P_66
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_strobe_in_n] ;## FMC_HPC0_LA02_N IO_L23N_T3U_N9_66
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx1_strobe_in_p] ;## FMC_HPC0_LA02_P IO_L23P_T3U_N8_66
set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_dclk_out_n] ;## FMC_HPC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_dclk_out_p] ;## FMC_HPC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_idata_out_n] ;## FMC_HPC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67
set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_idata_out_p] ;## FMC_HPC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_qdata_out_n] ;## FMC_HPC0_LA19_N IO_L23N_T3U_N9_67
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_qdata_out_p] ;## FMC_HPC0_LA19_P IO_L23P_T3U_N8_67
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_strobe_out_n] ;## FMC_HPC0_LA21_N IO_L21N_T3L_N5_AD8N_67
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_strobe_out_p] ;## FMC_HPC0_LA21_P IO_L21P_T3L_N4_AD8P_67
set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_dclk_in_n] ;## FMC_HPC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_dclk_in_p] ;## FMC_HPC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_idata_in_n] ;## FMC_HPC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67
set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_idata_in_p] ;## FMC_HPC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_qdata_in_n] ;## FMC_HPC0_LA19_N IO_L23N_T3U_N9_67
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_qdata_in_p] ;## FMC_HPC0_LA19_P IO_L23P_T3U_N8_67
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_strobe_in_n] ;## FMC_HPC0_LA21_N IO_L21N_T3L_N5_AD8N_67
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports rx2_strobe_in_p] ;## FMC_HPC0_LA21_P IO_L21P_T3L_N4_AD8P_67
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS} [get_ports tx1_dclk_in_n] ;## FMC_HPC0_LA07_N IO_L18N_T2U_N11_AD2N_66
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS} [get_ports tx1_dclk_in_p] ;## FMC_HPC0_LA07_P IO_L18P_T2U_N10_AD2P_66
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx1_dclk_out_n] ;## FMC_HPC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx1_dclk_out_p] ;## FMC_HPC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports tx1_idata_in_n] ;## FMC_HPC0_LA08_N IO_L17N_T2U_N9_AD10N_66
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports tx1_idata_in_p] ;## FMC_HPC0_LA08_P IO_L17P_T2U_N8_AD10P_66
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVDS} [get_ports tx1_qdata_in_n] ;## FMC_HPC0_LA05_N IO_L20N_T3L_N3_AD1N_66
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVDS} [get_ports tx1_qdata_in_p] ;## FMC_HPC0_LA05_P IO_L20P_T3L_N2_AD1P_66
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVDS} [get_ports tx1_strobe_in_n] ;## FMC_HPC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVDS} [get_ports tx1_strobe_in_p] ;## FMC_HPC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS} [get_ports tx1_dclk_out_n] ;## FMC_HPC0_LA07_N IO_L18N_T2U_N11_AD2N_66
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS} [get_ports tx1_dclk_out_p] ;## FMC_HPC0_LA07_P IO_L18P_T2U_N10_AD2P_66
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx1_dclk_in_n] ;## FMC_HPC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx1_dclk_in_p] ;## FMC_HPC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports tx1_idata_out_n] ;## FMC_HPC0_LA08_N IO_L17N_T2U_N9_AD10N_66
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports tx1_idata_out_p] ;## FMC_HPC0_LA08_P IO_L17P_T2U_N8_AD10P_66
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVDS} [get_ports tx1_qdata_out_n] ;## FMC_HPC0_LA05_N IO_L20N_T3L_N3_AD1N_66
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVDS} [get_ports tx1_qdata_out_p] ;## FMC_HPC0_LA05_P IO_L20P_T3L_N2_AD1P_66
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVDS} [get_ports tx1_strobe_out_n] ;## FMC_HPC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVDS} [get_ports tx1_strobe_out_p] ;## FMC_HPC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVDS} [get_ports tx2_dclk_in_n] ;## FMC_HPC0_LA22_N IO_L20N_T3L_N3_AD1N_67
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS} [get_ports tx2_dclk_in_p] ;## FMC_HPC0_LA22_P IO_L20P_T3L_N2_AD1P_67
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx2_dclk_out_n] ;## FMC_HPC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx2_dclk_out_p] ;## FMC_HPC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVDS} [get_ports tx2_idata_in_n] ;## FMC_HPC0_LA23_N IO_L19N_T3L_N1_DBC_AD9N_67
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVDS} [get_ports tx2_idata_in_p] ;## FMC_HPC0_LA23_P IO_L19P_T3L_N0_DBC_AD9P_67
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVDS} [get_ports tx2_qdata_in_n] ;## FMC_HPC0_LA25_N IO_L17N_T2U_N9_AD10N_67
set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVDS} [get_ports tx2_qdata_in_p] ;## FMC_HPC0_LA25_P IO_L17P_T2U_N8_AD10P_67
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVDS} [get_ports tx2_strobe_in_n] ;## FMC_HPC0_LA24_N IO_L18N_T2U_N11_AD2N_67
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS} [get_ports tx2_strobe_in_p] ;## FMC_HPC0_LA24_P IO_L18P_T2U_N10_AD2P_67
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVDS} [get_ports tx2_dclk_out_n] ;## FMC_HPC0_LA22_N IO_L20N_T3L_N3_AD1N_67
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVDS} [get_ports tx2_dclk_out_p] ;## FMC_HPC0_LA22_P IO_L20P_T3L_N2_AD1P_67
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx2_dclk_in_n] ;## FMC_HPC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx2_dclk_in_p] ;## FMC_HPC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVDS} [get_ports tx2_idata_out_n] ;## FMC_HPC0_LA23_N IO_L19N_T3L_N1_DBC_AD9N_67
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVDS} [get_ports tx2_idata_out_p] ;## FMC_HPC0_LA23_P IO_L19P_T3L_N0_DBC_AD9P_67
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVDS} [get_ports tx2_qdata_out_n] ;## FMC_HPC0_LA25_N IO_L17N_T2U_N9_AD10N_67
set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVDS} [get_ports tx2_qdata_out_p] ;## FMC_HPC0_LA25_P IO_L17P_T2U_N8_AD10P_67
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVDS} [get_ports tx2_strobe_out_n] ;## FMC_HPC0_LA24_N IO_L18N_T2U_N11_AD2N_67
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVDS} [get_ports tx2_strobe_out_p] ;## FMC_HPC0_LA24_P IO_L18P_T2U_N10_AD2P_67
# clocks
create_clock -name ref_clk -period 8.00 [get_ports fpga_ref_clk_p]
create_clock -name rx1_dclk_out -period 2.034 [get_ports rx1_dclk_out_p]
create_clock -name rx2_dclk_out -period 2.034 [get_ports rx2_dclk_out_p]
create_clock -name tx1_dclk_out -period 2.034 [get_ports tx1_dclk_out_p]
create_clock -name tx2_dclk_out -period 2.034 [get_ports tx2_dclk_out_p]
create_clock -name rx1_dclk_out -period 2.034 [get_ports rx1_dclk_in_p]
create_clock -name rx2_dclk_out -period 2.034 [get_ports rx2_dclk_in_p]
create_clock -name tx1_dclk_out -period 2.034 [get_ports tx1_dclk_in_p]
create_clock -name tx2_dclk_out -period 2.034 [get_ports tx2_dclk_in_p]
# Allow max skew of 0.5 ns between input clocks
set_clock_latency -source -early -0.25 [get_clocks rx1_dclk_out]

10
projects/adrv9001/zcu102/system_constr.xdc
View File

@ -1,6 +1,6 @@
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS18} [get_ports dev_clk_out] ; #FMC_HPC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_in_n] ; #FMC_HPC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_in_p] ; #FMC_HPC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66
set_property -dict {PACKAGE_PIN AA7 IOSTANDARD LVCMOS18} [get_ports dev_clk_in] ; #FMC_HPC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_out_n] ; #FMC_HPC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVDS} [get_ports dev_mcs_fpga_out_p] ; #FMC_HPC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports dgpio_0] ; #FMC_HPC0_LA16_P IO_L5P_T0U_N8_AD14P_66
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports dgpio_1] ; #FMC_HPC0_LA16_N IO_L5N_T0U_N9_AD14N_66
@ -39,6 +39,6 @@ set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports tx2_enab
set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS18} [get_ports vadj_test_1] ; #FMC_HPC0_LA31_P IO_L7P_T1L_N0_QBC_AD13P_67
set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports vadj_test_2] ; #FMC_HPC0_LA31_N IO_L7N_T1L_N1_QBC_AD13N_67
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx1_strobe_in_p]
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx2_idata_in_p]
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx1_strobe_out_p]
set_property UNAVAILABLE_DURING_CALIBRATION TRUE [get_ports tx2_idata_out_p]

154
projects/adrv9001/zcu102/system_top.v
View File

@ -52,12 +52,12 @@ module system_top (
input fpga_ref_clk_n,
input fpga_ref_clk_p,
// Device clock passed through 9001
input dev_clk_out,
input dev_clk_in,
input fpga_mcs_in_n,
input fpga_mcs_in_p,
output dev_mcs_fpga_in_n,
output dev_mcs_fpga_in_p,
output dev_mcs_fpga_out_n,
output dev_mcs_fpga_out_p,
inout dgpio_0,
inout dgpio_1,
@ -76,49 +76,49 @@ module system_top (
inout mode,
inout reset_trx,
input rx1_dclk_out_n,
input rx1_dclk_out_p,
input rx1_dclk_in_n,
input rx1_dclk_in_p,
inout rx1_enable,
input rx1_idata_out_n,
input rx1_idata_out_p,
input rx1_qdata_out_n,
input rx1_qdata_out_p,
input rx1_strobe_out_n,
input rx1_strobe_out_p,
input rx1_idata_in_n,
input rx1_idata_in_p,
input rx1_qdata_in_n,
input rx1_qdata_in_p,
input rx1_strobe_in_n,
input rx1_strobe_in_p,
input rx2_dclk_out_n,
input rx2_dclk_out_p,
input rx2_dclk_in_n,
input rx2_dclk_in_p,
inout rx2_enable,
input rx2_idata_out_n,
input rx2_idata_out_p,
input rx2_qdata_out_n,
input rx2_qdata_out_p,
input rx2_strobe_out_n,
input rx2_strobe_out_p,
input rx2_idata_in_n,
input rx2_idata_in_p,
input rx2_qdata_in_n,
input rx2_qdata_in_p,
input rx2_strobe_in_n,
input rx2_strobe_in_p,
output tx1_dclk_in_n,
output tx1_dclk_in_p,
input tx1_dclk_out_n,
input tx1_dclk_out_p,
output tx1_dclk_out_n,
output tx1_dclk_out_p,
input tx1_dclk_in_n,
input tx1_dclk_in_p,
inout tx1_enable,
output tx1_idata_in_n,
output tx1_idata_in_p,
output tx1_qdata_in_n,
output tx1_qdata_in_p,
output tx1_strobe_in_n,
output tx1_strobe_in_p,
output tx1_idata_out_n,
output tx1_idata_out_p,
output tx1_qdata_out_n,
output tx1_qdata_out_p,
output tx1_strobe_out_n,
output tx1_strobe_out_p,
output tx2_dclk_in_n,
output tx2_dclk_in_p,
input tx2_dclk_out_n,
input tx2_dclk_out_p,
output tx2_dclk_out_n,
output tx2_dclk_out_p,
input tx2_dclk_in_n,
input tx2_dclk_in_p,
inout tx2_enable,
output tx2_idata_in_n,
output tx2_idata_in_p,
output tx2_qdata_in_n,
output tx2_qdata_in_p,
output tx2_strobe_in_n,
output tx2_strobe_in_p,
output tx2_idata_out_n,
output tx2_idata_out_p,
output tx2_qdata_out_n,
output tx2_qdata_out_p,
output tx2_strobe_out_n,
output tx2_strobe_out_p,
inout sm_fan_tach,
output vadj_test_1,
@ -151,8 +151,8 @@ module system_top (
OBUFDS i_obufds_dev_mcs_fpga_in (
.I (dev_mcs_fpga_in),
.O (dev_mcs_fpga_in_p),
.OB (dev_mcs_fpga_in_n));
.O (dev_mcs_fpga_out_p),
.OB (dev_mcs_fpga_out_n));
// multi-chip synchronization
//
@ -207,45 +207,45 @@ module system_top (
.tx_output_enable (1'b1),
.rx1_dclk_in_n (rx1_dclk_out_n),
.rx1_dclk_in_p (rx1_dclk_out_p),
.rx1_idata_in_n (rx1_idata_out_n),
.rx1_idata_in_p (rx1_idata_out_p),
.rx1_qdata_in_n (rx1_qdata_out_n),
.rx1_qdata_in_p (rx1_qdata_out_p),
.rx1_strobe_in_n (rx1_strobe_out_n),
.rx1_strobe_in_p (rx1_strobe_out_p),
.rx1_dclk_in_n (rx1_dclk_in_n),
.rx1_dclk_in_p (rx1_dclk_in_p),
.rx1_idata_in_n (rx1_idata_in_n),
.rx1_idata_in_p (rx1_idata_in_p),
.rx1_qdata_in_n (rx1_qdata_in_n),
.rx1_qdata_in_p (rx1_qdata_in_p),
.rx1_strobe_in_n (rx1_strobe_in_n),
.rx1_strobe_in_p (rx1_strobe_in_p),
.rx2_dclk_in_n (rx2_dclk_out_n),
.rx2_dclk_in_p (rx2_dclk_out_p),
.rx2_idata_in_n (rx2_idata_out_n),
.rx2_idata_in_p (rx2_idata_out_p),
.rx2_qdata_in_n (rx2_qdata_out_n),
.rx2_qdata_in_p (rx2_qdata_out_p),
.rx2_strobe_in_n (rx2_strobe_out_n),
.rx2_strobe_in_p (rx2_strobe_out_p),
.rx2_dclk_in_n (rx2_dclk_in_n),
.rx2_dclk_in_p (rx2_dclk_in_p),
.rx2_idata_in_n (rx2_idata_in_n),
.rx2_idata_in_p (rx2_idata_in_p),
.rx2_qdata_in_n (rx2_qdata_in_n),
.rx2_qdata_in_p (rx2_qdata_in_p),
.rx2_strobe_in_n (rx2_strobe_in_n),
.rx2_strobe_in_p (rx2_strobe_in_p),
.tx1_dclk_out_n (tx1_dclk_in_n),
.tx1_dclk_out_p (tx1_dclk_in_p),
.tx1_dclk_in_n (tx1_dclk_out_n),
.tx1_dclk_in_p (tx1_dclk_out_p),
.tx1_idata_out_n (tx1_idata_in_n),
.tx1_idata_out_p (tx1_idata_in_p),
.tx1_qdata_out_n (tx1_qdata_in_n),
.tx1_qdata_out_p (tx1_qdata_in_p),
.tx1_strobe_out_n (tx1_strobe_in_n),
.tx1_strobe_out_p (tx1_strobe_in_p),
.tx1_dclk_out_n (tx1_dclk_out_n),
.tx1_dclk_out_p (tx1_dclk_out_p),
.tx1_dclk_in_n (tx1_dclk_in_n),
.tx1_dclk_in_p (tx1_dclk_in_p),
.tx1_idata_out_n (tx1_idata_out_n),
.tx1_idata_out_p (tx1_idata_out_p),
.tx1_qdata_out_n (tx1_qdata_out_n),
.tx1_qdata_out_p (tx1_qdata_out_p),
.tx1_strobe_out_n (tx1_strobe_out_n),
.tx1_strobe_out_p (tx1_strobe_out_p),
.tx2_dclk_out_n (tx2_dclk_in_n),
.tx2_dclk_out_p (tx2_dclk_in_p),
.tx2_dclk_in_n (tx2_dclk_out_n),
.tx2_dclk_in_p (tx2_dclk_out_p),
.tx2_idata_out_n (tx2_idata_in_n),
.tx2_idata_out_p (tx2_idata_in_p),
.tx2_qdata_out_n (tx2_qdata_in_n),
.tx2_qdata_out_p (tx2_qdata_in_p),
.tx2_strobe_out_n (tx2_strobe_in_n),
.tx2_strobe_out_p (tx2_strobe_in_p),
.tx2_dclk_out_n (tx2_dclk_out_n),
.tx2_dclk_out_p (tx2_dclk_out_p),
.tx2_dclk_in_n (tx2_dclk_in_n),
.tx2_dclk_in_p (tx2_dclk_in_p),
.tx2_idata_out_n (tx2_idata_out_n),
.tx2_idata_out_p (tx2_idata_out_p),
.tx2_qdata_out_n (tx2_qdata_out_n),
.tx2_qdata_out_p (tx2_qdata_out_p),
.tx2_strobe_out_n (tx2_strobe_out_n),
.tx2_strobe_out_p (tx2_strobe_out_p),
.gpio_i (gpio_i),
.gpio_o (gpio_o),