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ad_ip_jesd204_tpl_dac: Switch to sync arm toggling instead of setting only 

Added the second flip flop for timing reasons
main
Adrian Costina 2020-11-02 07:06:16 +00:00
parent c3465789b8
commit 7309da59d1
1 changed files with 4 additions and 2 deletions
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6
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
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@ -91,6 +91,7 @@ module ad_ip_jesd204_tpl_dac_core #(
wire [DAC_CDW-1:0] pn15_data;
reg dac_sync_in_d1 ='d0;
reg dac_sync_in_d2 ='d0;
reg dac_sync_in_arm ='d0;
reg dac_sync_d1 = 'd0;
@ -100,9 +101,10 @@ module ad_ip_jesd204_tpl_dac_core #(
always @(posedge clk) begin
dac_sync_d1 <= dac_sync;
dac_sync_in_d1 <= dac_sync_in;
dac_sync_in_d2 <= dac_sync_in_d1;
if ((~dac_sync_d1&dac_sync) == 1'b1) begin
dac_sync_in_arm <= 1'b1;
end else if ((~dac_sync_in_d1&dac_sync_in) == 1'b1) begin
dac_sync_in_arm <= ~dac_sync_in_arm;
end else if ((~dac_sync_in_d2&dac_sync_in_d1) == 1'b1) begin
dac_sync_in_arm <= 1'b0;
end else if (EXT_SYNC == 1'b0) begin
dac_sync_in_arm <= 1'b0;